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DRV8307: DRV 8307 driving 100%PWM when its pwm input is low

Ashwini Dongre
Prodigy 50 points
Part Number: DRV8307

We are using the DRV 8307 to interface to reciprocating piston pump.DRV 8307 is controlled by the FPGA.During testing we follow these steps:

1. Program the FPGA

2. Send 20% PWM-DC input to the DRV8307.We see the pump running at 20% PWMDC.Then reconfigure/reset the FPGA,(we expect the pump to stop).The pwm input of pump driver is low and pump stops.

3.Repeat steps 1 & 2 for for different PWMDC values(30%,40% upto 100%).

For all duty cycles except 100% ,the pump stops when FPGA is reconfigured or reset.This is expected,so no problem here.

The problem starts when 100% PWMDC input is sent to DRV8307 ,the pump starts running at 100% PWMDC.This is fine. Now press the reconfig/reset button on fpga board,we expect the pump to stop running.but pump doesn't stop.It continues running at 100% PWMDC,when FPGA image is not there.We probed the pwm output of FPGA(input of DRV8307) ,it is low.Then we probed the drive_en (active low) input of DRV 8307.It is low.We expect the pump to stop when the FPGA is reset/reconfigured,but pump continues to run at 100%PWM DC .This is happening only for 100%PWM DC.Any suggestions why?

  • 0
    TI__Guru** 114905 points
    Hi Ashwini,

    Please note the last sentence of section 7.4.1 of the datasheet date February 2016:

    When the DRV8307 is driving a motor, the motor should not be stopped by setting the PWM input to 0% duty
    cycle. Instead, ENABLEn should be brought high.

    If the device does not stop after ENABLEn is set to a high, would you please provide scope captures of the phase outputs and ENABLEn?
  • 0 in reply to Rick Duncan
    Prodigy 50 points

    Hi Rick Duncan,

    Thank you so much for the quick reply.

    We see that the pump stops running after enable_n is set to high.

    We have noted your point , we will use enable_n to stop the pump .

    I think a part of my question still remains unanswered.For all duty cycles except 100% ,the pump stops ,when FPGA is reconfigured or reset.(Please refer to my original description).

    The enable_n input of drv8307 is low in all the cases. The pump doesn't stop only at 100% PWMDC .Why do we see this behaviour only at 100% PWMDC?

    Regards

    Ashwini Dongre

  • 0 in reply to Rick Duncan
    Prodigy 50 points
    Hi Rick Duncan,Thank you so much for the quick reply.
    We see that the pump stops running after enable_n is set to high.
    We have noted your point , we will use enable_n to stop the pump .
    I think a part of my question still remains unanswered.For all duty cycles except 100% ,the pump stops ,when FPGA is reconfigured or reset.(Please refer to my original description).
    The enable_n input of drv8307 is low in all the cases. The pump doesn't stop only at 100% PWMDC .Why do we see this behaviour only at 100% PWMDC?
    RegardsAshwini Dongre
    I am not sure how to reply to your post.The reply is coming back to me.
  • 0 in reply to Ashwini Dongre
    TI__Guru** 114905 points
    Hi Ashwini,

    We are glad to hear the pump stops after enable_n is set to high.

    We will have to investigate why the pump doesn't stop at 100% PWM. This may take a few days.