DRV8305: Delay time

Takao Yamamoto

Genius 4135 points

Part Number: DRV8305

Dear all,

■Propagation delay

How long does this take from INHA to GH_A? And how long does this take from INLA to GL_A?

Are these 200ns? But how is the worst condition? Should we add 'tpd_match' = 50ns?

■PWM propagation

We input PWM through 12.2ns intervals.

This device can propagate 12.2ns intervals directly, can't this?

*We consider if there are some timer or logics to expand delay time.

■Behavior

If we input faster pulse than Fgate=200kHz, what behavior does this act?

Best regards,

over 8 years ago

0 Luis Riveros over 8 years ago

TI__Expert 4435 points

Hello Yamamoto-san,

- The INHA to GH_A is 200ns. I will get back to you for INLA to G_LA and worst condition.

- Could you please explain further the PWM propagation question? Is the 12.2ns the high time of the pulse?

- For the behavior question, the maximum recommended Fgate is 200kHz. The behavior is dependent of the FETs in application and current through them.

Thank you.

0 Takao Yamamoto over 8 years ago in reply to Luis Riveros

Genius 4135 points

Hello Riveros-san,

Thank you for your reply.

- When could you answer about INLA to G_LA and worst condition?

- Sorry for confusing you. 12.2ns is cycle time.
If DRV8305 has something timer or logics, DRV8305 may take more time to output than 12.2ns.
*This is my imagination. I think that DRV8305 can output 12.2ns without change, but I checked this just to be sure.

Best regards,

0 Luis Riveros over 8 years ago in reply to Takao Yamamoto

TI__Expert 4435 points

Hello Yamamoto-san,
for the 12.2ns, could you please show a timing diagram for your question for better understanding and support. Thank you very much.

0 Takao Yamamoto over 8 years ago in reply to Luis Riveros

Genius 4135 points

Hello Riveros-san,

Thank you for your reply, and sorry for my late response.

For more detail condition, I am checking my customer about '12.2ns'.
By the way, how is the progress about INLA to G_LA and worst condition?

Best regards,

0 Luis Riveros over 8 years ago in reply to Takao Yamamoto

TI__Expert 4435 points

Hello Yamamoto-san,

For the INL_A to GL_A delay, I have forwarded question to designer. It should be the same as the high side but I am waiting on confirmation. Thanks.

0 Takao Yamamoto over 8 years ago in reply to Luis Riveros

Genius 4135 points

Hello Riveros-san,

Thank you for your support.

About propagation delay, I would appreciate if you inform when you could answer.

About PWM propagation, I am sorrry to confusing you. I checked my customer and some update.

Please look at following PDF file. I wrote question and backgroung.

PWM propagation.pdf

Best regards,

0 Luis Riveros over 8 years ago in reply to Takao Yamamoto

TI__Expert 4435 points

Hello Yamamoto-san,

Thank you very much for the diagram I understand the question now.

For the propagation delay question:
I have confirmed that low side delay is similar to high side delay 200ns.

For the PWM propagation question:
- The output waveform will have a slight variation if your resolution is 12.2ns. This is due to the internal core logic.
- There is an internal 25Mhz glitch clock, so the variation would come from the moment PWM switches high/low or low/high to the next sampling of the glitch clock which is every 40 ns.

0 Takao Yamamoto over 8 years ago in reply to Luis Riveros

Genius 4135 points

Hello Riveros-san,

Thank you very much for your answer. And I am sorry for my confusing English.

About the propagation delay,
How long should I think the margin to design over temperature?
200us is typical value. Should I think this delay plus 50ns like dead time? or more?

Best regards,

0 Luis Riveros over 8 years ago in reply to Takao Yamamoto

TI__Expert 4435 points

Hello Yamamoto-san,

The value should be close to 250us yes. Remember that these are typical values at 25C. Thank you.

0 Takao Yamamoto over 8 years ago in reply to Luis Riveros

Genius 4135 points

Hello Riveros-san,

Thank you for your answer, but could I re-check my idea?

I have understood that 250ns is typical value.
However, I would like to know how margin should I think?
Is '250+50=300ns' enough to think margin over temperature?

Best regards,

0 Luis Riveros over 8 years ago in reply to Takao Yamamoto

TI__Expert 4435 points

Hello Yamamoto-san,

300ns should be okay yes. Thank you.

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DRV8305: Delay time