DRV8305: device danaged more times with AVDD 0V after crash

Hello,

Thank you for the information.

How much current is being pulled out of the VREG pin when nFAULT begins to toggle?

What devices are supplied by VREG in your application?

Are you able to read back the SPI registers when nFAULT begins to toggle in your application?  This would tell us which FAULT is indicated over the FAULT pin.

Hello,

I appreciate the detailed information, this is very helpful for our debug.

Could you share a schematic of how you're using the DRV8305 devices?  Specifically I'm interested in how you have the ground pins connected on our device and any external circuits.

I uploaded the schematics. Im not sure if you see that. I try it again after my comments.

You see it is the circuit from the datasheet proposal.

I drive the board via  the edge connectors with an atmel Mega2656 controller. It delivers the PWMs the SPI communication and reacts to nFault and PWRgood with stopping the PWMs.

The software runs in 3-PWM mode. The free 3 Lowgates are steadyly programmed to 0V.

The connection of both grounds and VREG happens at the control connector P5, where GND is shortly conected to the goundplane . VREG is layouted to the connector (distance about 2 cm).

How I can post an schematic ?

Bye Tetrastruct.

Motorsteuerung.pdfBottom.pdfBottom.pdfTOP.pdf

When I have my repaired boards back, I will monitore the SP+/SP- Voltage under test and trace the spi MISO datas after triggering the active nFault condition.

What about the critical short time peak of the Sense Input voltage ?

Hello,

You see, uit seems a problem caus you are the third case with this problem.

to Phil :

What i the typical load, the IC is made for ?

When you have such unsymmetrical input ranges between S+ and S- you can not so good use the sense signal at RL-loads to PGND because you will always measure a negativ voltage caused by the freewheel current through the shunt and the  lower transistor ( or freewheel diode).In the other case at RL-Loads to VDD you measure the rising current through the lower transistor an the voltgae S+/S- is always positive an can get ranges until 5 V. That means Loads to ground will reach the limit at 40 % against loads to VDD.

My load was against PGND and the AVDD brokes at ca 30 A, that means the bad case if the resistors will grow up with temperature and some dynamical peak currents could reach the Input voltage of -2 V

Is there a solution to protect these Inputs ?

today I got my repaired boards.

I will carefully monitor the S+/S- Inputs in further tests.

In the positive range It seems not the problem cause of the huge current which leads to 5V but also a Diode to VREF would give more trust. at the nagative side maybe 5 Diodes in serie from PGND to SP-  could help.

Hi Phil,

Got back my boards.

I Tried to stimulate the errror

1) Measured a RL load (15 mOhm 20uH) against +VDD and had no errors from 0 until 15 A.Switching Freq. 16 MHz PWM ca. 98 %.

The current sense signal was regulare. I measured the rising current in the shunt. No problems.

2) I measured the sam RL load against PGND.

The error happened very quick and showed me the pre status of the device killing.
It begins with periodically lowwing nFault with a duration of ca. 750us.
Cause of that the gates will closed and adter ca 1 ms the gates are switched again as long as it happens again.
This effect leads to a brubbling noise in the motor. It strts at currents of about 3..4 amps and become mor and more peroodically.

What happens at this event ? 

In datas of SPI there is absolutely nothing shown nor flag alll the status flags are 0.
I checked this with th Logig analyser . I will upload the screenshots.
One thing is totaly strange:

I measured the SP+/SP- Voltage parallel to this behavior.
The SP+ voltage was the whole time normal in a range of about -30 mV rising down after switching off t0 -30 mV and slowly rising up to 0 V cause of freewheeling. Shortly before the nFault event happens
the SP+ Voltge began progressively to fall down to about -100mV in a strange way (see screenshots). Then the nFault happens, the gates will closed for 2 ms and so on.
Nothing happens with the SPI.
This was at ca 5A. In former tests I ignored this and opened the PWM. The result was a damaged AVDD.

Here are the picture:

You see her the SÜP+ voltage befor nFault become activ for 750 us. You can see SP+ is the whole time normal at ca 50 mV

When this happens, the spikes at SP+ reach progressive an dynamical Value of ca -8V

Here you see:

green:SP+

yellow: The FET Halfbrigde output

DO: nFault

D1: _CS SPI

D2: Clk SPI

D3: MISO SPI

MISO: Decoded Datas SPI   REG 0xC...... ROG 0x1

________________________________________________________________________________________

The Mainquestion is: Why the nFault signal became activ ? and why was absolutely no recognition o these situation by  the Error and report management ?

The tempratures were in the region of about 60°C

The shunt resistors are 10 mOhms and the voltage of 30...50 mV is quite normal for the current of 5 A.

No program change at the shunt register or sense register had any influence to this interrupting behavior.

Hi Phil,

Watching my screenshots carfully I see, that with the error begins a switching of the freewheel track. When you lock at the normal FET signal you see always 

during freewheel period a small negative output voltage always whwn the freewhell path is active. Thias results while the body diode is freewheeling.

Is it so that the driver begin to switch to synchronous rectifieing ??? at a special current.

It seems that the time constant switches to a higher value cause of a lower freewheelrestistance. Is it possible tha the lowside is switching the fet for synchronous rectifieing.

I cant see during this error behaivior the typical negative freewheel voltage drop at the fet outputs the fet outputs are nearly 0 and have mayby only the shuntvoltage a snegative offset.

That means that freewheeling must happen over the low-Fet with lower resitance.

But why cause that  nFault and why will the spikes at SP+ so drastically increase to negative values ? 

Hello,

Here is my suggestion:

1. The -8V on SP+ is most likely causing damage to our device and could be causing several other blocks in our device to be damaged.  I would recommend doing the following.
   1. When nFAULT goes low, what is the voltage on DVDD, AVDD, and VREG?  Do any of these show abnormal behavior during the nFAULT event?
   2. When nFAULT goes low, what is the voltage different on the low-side MOSFET that is being turned on?  This could be causing a VDS fault on our device.
   3. What is the duration of the -8V spike measured on SP+?  Are you able decrease you time scale and trigger on the falling edge of nFAULT?  This would give us a clear picture of how long the -8V spike is present on SP+ and for how long this transient is greater than the abs. max of our part.
2. For your application, if you tie SP+ to ground (bypassing your sense traces), does this behavior disappear?  
3. If you replace your sense traces with larger sense resistors, does this behavior disappear?
4. Can you read just the 0x01 STATUS registers during the nFAULT Low event?  
5. If you use a smaller V/div scale on the SHx out put (yellow trace in your scope capture), how negative does SHx when the RL circuit is freewheeling?

If the -8V Spikes are due to the inductive EMF pulling the SP+ node down, this will cause damage to the shunt amplifier.

Hi Phil,

Thansk for your information and suggestions. What do you comment about diode protection about SP/SN pins? Do we face any side-effects of using TVS between these pins?

Regards,

Eray CANLI

Hi Phil,

Thank you for your hints.

I made new measurements.

I did not destroy the device today but I found out that the begin of the described nFault activity  is correlated to the Current value in the FET.

1) This effect only happens, when the RL load is switched against PGND, never at loads against PVDD

2) The effect is anticorrelated with the programmed positive Gate current at the HIGH side switch. It happens when the programmed current is to high
     have you any description for this ?

     I have to switch  two IRFS3107  FETS. At about 20 A FET current the nFault begins periodically to become active.no other information in the SPI.
     The programmed Gate current was at 0,75A. I could eliminate this effect by more and more reduction the programmed Gate current at the high side.

     When I reduced it to 70 mA I could reach about 50 A in the FETS (load against GND).

     The spikes at the SP-/SP+  are at a frequency of about 24 MHz. Pulses with higher energy I did not recognice at these pins.

     The measured voltage represented the current at these resistor. That was everything normal.

3) My question:  Is your device able to drive 150 A FETS.
    Is there a limit regarding the gate charge capacities of the FETS which are to drive with drv8305

   Why will the device begin to make trouble at loads to PGND with a higher programmed  positive Gate current. I assumed The FET would be switched quicker, but I got more stable
   running device by reducing the + Gate current at the high side ?
   The reduction of these Current made the switch ON edges very low in an range of over 500 ns, while the OFF edge was still in the 50 ns range.

Hi Phil,

I think that will the last comment regarding  this post cause I get no more answers to my problem.

I tested the new repaired boards and got the same strange errors of the chip.

Following facts  I can comment:

1) The effect happens independent to the current measurement. It has nothing to do with SP+ /SP- voltage. I shorted the signal.

2) The divice was destroyed at a VDD of 20 V and reaching a current oof 25 A of an RL Load to PGND only.

3) The result of destroying was AVDD was 0V after crash. Alle Voltages VREG AVDD and VDD were in a normal good range during fault

4) The precrash began with preriodic strange Output pulsform. After that nFAUKT went down for 750 us without ! any notification in the SPI datas.

5) During nFAULT  AVDD always went to 0V.

6) The effect began at currents over 10 A and dissapointed  again at currents of about 20A. (Only in a windowed region)

7) the effect could be moved to higher current regions by reducing the HIgside positiv gatecurrent to lower values. I coud definitely stimulate ans stabliise  the error by increasing  the positiv Higside gate current.

8 Lowside control had no Influence.

9) negativ Higside current had no influence to the erorr.

10) I seems that the error was also synchron triggered from  the SPI burst package everey 25 ms . (May be e ringing effect )

magenta : nFault

green: AVDD

yellow: OUTPUT signal

azur: current

green: SPI Datas

green AVDD

magenta nFaULT

azur  current

yellow output pulses

changed output form shortly befor error.  See the zoomed region

You see wrong switching behaivior shortly bvefor nFAULtt becomes active.

I think tha  I will propose my customers not to work with this 8305 for further applications as long this undescribable strange behaivior is not cleared finally.

Questions:

1) is the driver capable to drive 150 A FETs at 48 V ?

2) Has the running SPI any possible influence to the operation of Gate controlling in what ever circumstances ?

3) Are tere limitations regarding Gate charge of the FETs

4) describe why AVDD is going down during nFAULT

Regards 

Prof. Müller-Syhre