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DRV8301: DRV8301 showing no fault still not working

Jesal Patel
Intellectual 840 points
Part Number: DRV8301

Hello there,

I've been working with communicating  LaunchXL28069 with DRV8301 (we designed the driver hardware) via SPI .

The FAULTn and OCTWn pins shows logically "1" during power up, and it goes off when program is in debug mode.

The EN_GATE shows transition from LOW -> HIgh.

PROBLEM:

there is no signal seen on gate of the MOSFETS.

the SPI_CLK is not showing up Clock signal.

the SDO and SDI are also not showing up.

  • 0
    Intellectual 840 points
    Can anyone send me the procedure to test the SPI registers via code?
  • 0 in reply to Jesal Patel
    TI__Guru** 114905 points
    Hi Jesal,

    Is your problem with the DRV8301 or the LaunchXL28069? If SPI_CLK is not showing up, this appears to be a problem with the LaunchXL28069.

    The procedure is listed in the datasheet starting at section 7.5.1

    I suggest you focus on reading register 0x2, which should reply with 0x200

    Also please note section 7.4.1: SPI communication is supported when EN_GATE is low.
  • 0 in reply to Rick Duncan
    Intellectual 840 points

    Hello Rick,

    Sir, I've successfully tested LAUNCHXL28069 which worked well. I tried with the procedure you described watching DRV_Ctrl register 0x2 which showed 0x0000. Also regarding the EN_GATE, i refered the datasheet which reads

    I also tried capturing the SDI  = CH_2 waveform

    ,SDO = shows no output (always remains HIGH) , SCS  = CH_1 waveform

    SCK shows up in CH_2; SCS in CH_1

    I had some problems with DRV8301 earlier which lead me to replace the IC ,so i've soldered a new one, can you please tell me regarding the chances of DRV8301 IC getting damaged?

    and how can i ensure that?

  • 0 in reply to Jesal Patel
    TI__Guru** 114905 points
    Hi Jesal,

    Do you have a solid ground connection to the power pad of the DRV8301? This can cause many problems if the connection is not there.

    Have you set EN_GATE high and confirmed the regulators are powered up properly and the fault pin is de-asserted?
    Do you have power at VDD_SPI?

    Also please read the register twice. This is required to obtain the proper data. From the datasheet:

    For a READ command (Nth cycle) sent to SDI, SDO will respond with the data at the specified address in the next cycle. (N+1)
  • 0 in reply to Rick Duncan
    Intellectual 840 points

    Hello Rick,

    Yes I soldered the powerpad , but i've got no way to check as it is benith the IC .

    I also checked the EN_GATE  = 'HIGH" and both regulators poweredup properly.

    VDD_SPI = 3.3V [checked]; when READ command (Nth cycle) sent to SDI, SDO remains "HIGH" even after (N+1) cycle.

    can you please share me the snap of the memory window which is to be checked. 

  • 0 in reply to Jesal Patel
    TI__Guru** 114905 points
    Hi Jesal,

    Sorry, I missed the fact that nSCS was low through out the two transactions. At the end of 16 clocks, nSCS should be set to a logic high to frame the transaction.

    Please see the post: e2e.ti.com/.../1723924 as an example.

    The datasheet also describes a valid SPI frame in the SPI section.