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DRV8711: External FET Selection

DO-Pro
Intellectual 610 points
Part Number: DRV8711
Other Parts Discussed in Thread: CSD18531Q5A,

Hi,

I'm going through the DRV8711 datasheet and have some confusion regarding the equation (3) in the section 7.3.9, External FET Selection.

It's generally clear that this equation governs the relationship between maximum acceptable gate charge Qg of the selected MOSFET and the configuration settings of the chip itself. However, some of the parameters included are somewhat unclear. What is a '20mA' constant? Apparently it's some kind of the value of some current, but which one? Why is '2*DTIME' involved? What does '4' constant in denominator signify? And more questions could possibly follow...

So, summing up, would it be possible to provide some background on this equation and explain the science and reasoning behind it in more details?

Thank you, Michael

  • 0
    TI__Guru** 114905 points
    Hi Michael,

    2*DTIME + TBLANK + TOFF is calculating the maximum PWM frequency. The 4 is the number of high side FETs driven by the charge pump.

    I am trying to confirm the 20mA, and should have an answer in a day.
  • 0 in reply to Rick Duncan
    TI__Guru** 114905 points
    Hi Michael,

    The 20mA is the DC charge pump current capability. We will add this to a future datasheet update.
  • 0 in reply to Rick Duncan
    Intellectual 610 points
    Rick,

    Thank you! Both answers are very informative.

    I also have a question regarding overcurrent protection of the external FETs. To be more specific let's take a look at the part used on DRV8711EVM board - CSD18531Q5A. According to its datasheet, the Rdson = 3.5 mOhm typ and default settings for EVM board are OCPTH = 00 (that is the OCP threshold is 250mV) and OCPDEG = 00 (that is the OCP deglitch time is 1 us).

    Now let's consider situation when output of the half-bridge is dead-shorted to the power rail Vm and the bottom MOSFET of that same half-bridge is commanded ON. The current floating in the bottom MOSFET under such conditions is similar to the shoot-through current and its value is limited by the Vm source's output impedance, circuit parasitics, FET's Rdson, and sense resistor's value. So this current could be quite high. And for the settings mentioned above it would be about 250mV / 3.5 mOhm = 71.4 Amp spike. Sounds a little extreme for the small device rated for 19 A with typical copper footprint.

    So the questions are below.

    1. Is such a spike actually safe for CSD18531Q5A device? Or is that too much and OCP won't be able to protect FET under such conditions?

    2. If such a spike is OK, what parameter should I look for in the FET's datasheet to ensure its safety? Is that Idm, Pulsed Drain Current, under Absolute Maximum Ratings table, page 1?

    3. And more generic question. What's an anticipated response time of the OCP circuitry once OCP deglitch timer has expired?

    Thanks, Michael
  • 0 in reply to DO-Pro
    TI__Guru** 114905 points
    Hi Michael,

    For questions 1 and 2, we will contact the FET experts.

    For question 3, we will check and get back to you.
  • 0 in reply to Rick Duncan
    TI__Mastermind 18200 points

    Michael,

    Whether or not the FET can handle this pulse depends on both the FET's pulsed current ratings (to which you can refer to the horizontal lines in the SOA), but also the thermal environment of your board. 

    The longer the pulse duration, the more the thermal environment (PCB thickness, ambient temperature, airflow, etc...) matters. The shorter the pulse duration, the more it comes down to the internal makeup of the device (i.e. the ratings in Figure 10). 

    The critical question is how long do you expect this pulse to last?

  • 0 in reply to Brett Barr1
    Intellectual 610 points

    Hi Brett,

    Since we're talking here about emergency over-current condition, the lasting time of the pulse would mostly depend on Deglitch Time setting of DRV8711 controller. The worst case for that setting is 8us so I would say it should last no longer than 10us total. Is that something that selected FET will handle?


    Thank you, Michael

  • 0 in reply to DO-Pro
    TI__Mastermind 18200 points
    Michael,
    For such short pulse duration, I don't think that should be a problem at all. You can refer to the pulsed current rating IDM, which suggests that the part can handle up to 370A for up to 100us.

    You could also use the transient thermal impedance curve to calculate what the delta T will be for this pulse. I wrote a blog about how to calculate pulsed current limitations. For 10us, all the heat dissipation will be local, so we really only have to worry about Rth junction to case, not Rth junction to ambient.

    e2e.ti.com/.../understanding-mosfet-data-sheets-part-4-mosfet-switching-times
  • 0 in reply to Brett Barr1
    Intellectual 610 points

    Brett,

    Thank you for detailed explanations.
    I think my questions 1 and 2 are now answered.

    Michael

  • 0 in reply to DO-Pro
    TI__Guru** 114905 points
    Hi Michael,

    3. And more generic question. What's an anticipated response time of the OCP circuitry once OCP deglitch timer has expired?

    The design team says the delay should be <100ns.
  • 0 in reply to Rick Duncan
    Intellectual 610 points
    Rick,

    Thank you.
    My questions are all answered now.

    Michael