DRV8305: Problem on nFault and GHA output

Hi Tao_2199,

Tao_2199 said:

(1) When they configured VREG and EN_GATE at power on, nFault is toggled with about 64us period.

(It seems that when EN_GATE is high, nFault stop to toggle and goes to high.)

Please attached file.

According to datasheet(page32:7.4.1 Power Up Sequence),

"nFAULT will be driven low to indicate that the device has not reached the VPVDD_UVLO2 threshold."

In case of thier application, nFault output is correct? Or something problem is happened while power on?

Was the SPI register read to determine the cause of the warning? What value was read?

What cause the nFAULT to stop toggling?

Tao_2199 said:

(2)When INH and INL are set Low at starting motor drive, GHA output is not Low. (It’s High.)

Please attached file.

Is it correctly operation? Can GHA be set as Low(0V)  at INH/INL=Low?

Please note section 7.2 of the datasheet. When GHx is low, this means the VGS voltage across the high side FET = 0. The high side gate is connected to the phase pin.

Hello Rick,

Sorry for delay.

>Was the SPI register read to determine the cause of the warning? What value was read?

>What cause the nFAULT to stop toggling?

(Answer)

SPI register isn’t read while nFAULT is toggling.

And I’m asking about cause of the nFAULT stop toggling.

(Question)

(1)While the nFAULT is toggled, EN_GATE is Low(standby state).

Is SPI I/F available while this state?

(2)Also they confirmed Power-Up with DRV8305 EVM and

the signal of nFAULT is toggling same as their application.

(SPI register isn’t read while nFAULT is toggling.)

Please refer below wave capture.

What do you think about cause the nFAULT to stop toggling?

> Please note section 7.2 of the datasheet. When GHx is low,

>this means the VGS voltage across the high side FET = 0.

>The high side gate is connected to the phase pin.

(Question)

(3) I can understand that when GHx is Low, high side FET =Low,

But when INHx and INLx are Low, I can't make clear why GHx is Low at their application.

Could you please explain about this point in detail?

(Additional question)

(4) About Power-Up sequence(fuger15)

Could you please tell me Power-Up sequence with EN_GATE and VREG in detail?

(Timing)

･PVDD supply -> VREG supply : Wait  ? ms  for interval ?

･nFault=High ->EN=High : Wait  ? ms  for interval ?

･EN=High -> INH/Lx input command : Wait  ? ms  for interval ?

(5)According to Figure 15 in datasheet,

The nFAULT stop toggling.by PVDD(logic threshold),

and goes to High by PVDD(PVDD_UVLO2).

So these are controlled internally at Power-Up sequence.

My understanding is correct?

Regards,

Tao2199