DRV8305: nFAULT at startup of DRV8305

Hi Masami-san,

Customer might have experienced a warning event. During a warning event, the nFAULT pin pulses low for 56usec and then high for another 56usec. This is described in detail in section 7.3.8 in datasheet, Table 5 shows all faults and warning modes.
This would not show as a fault in the status register but as a warning (address 0x1). The bit would report an specific type of warning. Please try reading this address. Thank you.

Luis-san,

Thank you for your reply.
But the customer also confirms warning when the pulse of nFAULT signal is output.
Neither fault nor warning (address 0x1) was on at the first status reading.

Thanks, Masami M.

Luis-san,

Thanks for your support.
The customer confirmed the following.

The reason why warning (address 0x1) is not displayed in the status read is as follows.
- EN_Gate remained Low at power on. After this, it seems that PVDD UVLO was on.
- The interrupt handling SW initially made EN_Gate High. At this time nFAULT seems to be clear.
- Status reading was executed after that and FLG was not on stand.

Therefore, please tell me.
When EN_Gate is changed from Low to High, nFAULT is cleared and FLG of the status register is cleared. Is the operation correct?

Thanks, Masami M.

Hi Masami -san,
What is the PVDD voltage when EN_Gate switches from low to high.
Could you please confirm power up sequence? A diagram would be very helpful. Thank you.

Hi, Luis-san,

Thanks for your support.
I drew a diagram of the power up sequence.
Please look at it.

Thanks, Masami M.

Michino-san,

Thank you for the diagram. I will check this condition and reply back soon.

Hi Michino-san,

I apologize for the late response.

Could you please provide PVDD ramp rate? Also, before pulling EN_GATE high, can you try to read when nFault pin in the toggling condition? what does the fault read? This should also clear the toggling. Please see diagram for clarity. Thank you.

Hi, Luis-san,

Thanks for your support.
Please wait for a while as we will check with the customer.

Thanks, Masami M.

Hi, Luis-san,

Sorry for the late response.
A response came from the customer.

> Could you please providing PVDD ramp rate?

About 3V/mS

> Also, before pulling EN_GATE high, can you try to read when nFault pin in the toggling condition?
> what does the fault read?

During this time, the customer is not leading the status. nFault pin is toggling.
However, if they stop the program at this timing and read the status register, they can confirm that Fault Status is On.

If they read the status register after EN_Gate is set to On, Fault Status is cleared.

Thanks, Masami M.

Hello Michino-san,
I apologize for the delayed response. I overlooked at this thread. This is a known behavior of the DRV8305 device. Fault toggling will go away once EN_GATE is enabled. Thank you.

Hi, Luis-san,

Thank you for your answer.
I reply the customer by this result.

Thanks, Masami M.