DRV8432: DRV8432 driving 2 TEC

Hi Jon,

That means, PWM_A and PWM_B will drive the 1st full H-bridge, and PWM_C and PWM_D will drive the 2nd full H-bridge. Right?

>> For section 7.4 of the datasheet:
In mode 1 and 2, PWM_A controls half bridge A, PWM_B controls half bridge B, and so forth Figure 8 shows an application example for full bridge mode operation.

But there is no detailed information about the full H-bridges in the datasheet. Is one full H-bridge consist of 2 N-channel MOSFET and 2 P-channel MOSFET?

>> All output FETs are N-channel, which is why there is a bootstrap capacitor needed.

The reason for this is, I'm not clear about how to drive PWM_A and PWM_B. For my understanding:

If PWM_A =1 and PWM_B = 0, TEC will work (for example) in heating mode;

If PWM_A =0 and PWM_B =1, TEC will work in cooling mode;

If PWM_A =0 and PWM_B = 0(Or PWM_A =1 and PWM_B =1), TEC will not work. Am I correct?

>> You are correct.

If so, I can just PWM-ing PWM_A and drive PWM_B low to control the heating level. But after checking other threads, it seems that one small pulse should appear on PWM_B in every period to charge bootstrap cap. Is it correct?

>> This is incorrect. You need a small pulse on PWM_A to charge the bootstrap cap, or to recover from a CBC current limit.

And if so, what is the right time slot for the pulse on PWM_B? At the same time when PWM_A goes to high? Or when PWM_A goes to low? Do you have any diagram/picture to illustrate this?

And I also see in some applications, PWM_B is complementary of PWM_A. What is this for? This makes me confused a lot.

Hi Rick,

Thanks a lot for your quick response :)

All output FETs are N-channel, which is why there is a bootstrap capacitor needed.

-->Jon:If all FETs are N-channel, do we need to consider the dead time between PWM_A and PWM_B?  And I also see in some applications, PWM_B is complementary of PWM_A. What is this for?

This is incorrect. You need a small pulse on PWM_A to charge the bootstrap cap, or to recover from a CBC current limit.

->Jon: In mode 1, does only PWM_A need a small pusle? Or PWM_B also needs it?

Thanks in advance.

BR

Jon

Hi Jon,

-->Jon:If all FETs are N-channel, do we need to consider the dead time between PWM_A and PWM_B? And I also see in some applications, PWM_B is complementary of PWM_A. What is this for?

>>> There is no need to consider dead time. Dead time prevents the high side FET and the low side FET of the same output being on at the same time. This is controlled internally. When using parallel mode, there is a need to add inductors or ferrite beads to prevent the two outputs conflicting with each other.
>>> This is dependent on the application. In stepper motor applications, using complementary outputs changes the speed that current can be removed from a winding.

->Jon: In mode 1, does only PWM_A need a small pusle? Or PWM_B also needs it?

>>> It is recommended to provide a small pulse to PWM_B also. This is required to reset the cycle by cycle operation if activated. Please refer to section 7.4 "Device Functional Modes" for details.