Question from customer:
We had a question regarding the predriver watchdog timeout.
While performing a test to stop petting the watchdog we notice the timing to shut off the output is 43ms when WD_DLY is set to 50ms.
When updating the WD_DLY value to 100ms, the timeout occurs in 87ms.
Do you know what is causing this skew, is it intended or is it a tolerance of the internal clock ~15%?
