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DRV595: discrepancy between SYNC and switching frequency

Sukwon Yoo
Prodigy 70 points
Part Number: DRV595

Hello,

I am using DRV595 to drive a TEC (+/-4V, 3A MAX).

First, the driver was configured to be in 20dB, SLV mode. The SYNC input was 1Mhz. Also, FS0,1,2 were set to [1 1 0], 1Mhz. 

When I enabled the chip with 0 differential input, the chip got really hot consuming 5W without any load attached. I measured output (+/-) signals and there were unsynchronized 4.3Mhz signals out from output pins (drive side of inductors).

Then, I changed the mode configuration so that the chip could be in the 20dB/Master mode and disconnected the SYNC input (floating). (No changes in FS 0,1,2 configuration, still in 1Mhz config).

The output signals were 1Mhz which I expected, BUT the SYNC signal (now its an output) was 100kHz! Ah-ha! 

I switched it back to the 20dB/SLV mode and NOW with 100kHz SYNC input! Then, the output signal was 1Mhz and there was no excessive power consumption.

Based on these experiments, It seems there is a factor of 10 in between the SYNC and output signals.

Now, I have two questions.

1.   I couldn't find any mention of this factor of 10 between SYNC and output signals in the datasheet. Is this expected feature? or is this something that we can set with FS pins?

2.  In SLV mode, do FS pins need to be set correctly? meaning that does it need to be matched with input SYNC? 

Thanks,

Sukwon

  • 0
    TI__Mastermind 24835 points
    Hi Sukwon,
    Your experiment result is expected. If only one device is used in your your application, please use it in master mode. And if more than 1 deivces are used and you really want to sync them, you could set one device in master mode and the others in slave mode(you could also set all of them into master mode). And the master output clock is connected to the sync clock input on the slaves. Usually the number of the slaves is less than 5. Please don't use the external sync clock(only from master sync clock output) for slave mode device. In both slave mode and master mode, FS pins need to be set correctly.
    Best regards,
    Shawn Zheng
  • 0 in reply to Shawn Zheng
    Prodigy 70 points
    Hello Shawn,
    1. Is there a reason why we shall not drive the device with external sync signal? I am using external sync signal from on-board FPGA (Not from other DRV595) to sync the device and it's working fine so far.
    2. What is the correation between SYNC input to switching frequency? Is the factor of 10 (SYNC 100kHz -> 1Mhz Switching) default? or is this something that we can change?
    3. For those FS pins, what do you mean by setting correctly? For example, if the deivce is in Master mode and getting 100kHz Sync signal to get 1Mhz switching frequency, what would be a correct configuration for the FS pins? Is FS pin configuration completely independent to the switching freqnecy if it's in Master mode?

    Thanks,
    Sukwon
  • 0 in reply to Sukwon Yoo
    TI__Mastermind 24835 points
    Hi Sukwon,
    Thank you for the reply. That the external sync input is not recommended is due to safty, performance and reliablity consideration. A bad SYNC clock could cause the performance loss and instability. The SYNC clock is ~100kHz, and the correct way to change the slave output PWM clock frequency is to program the voltage on FS0~FS2 instead of changing SYNC clock frequency. The table on Page 5 in the datasheet shows the relationship between PWM frequency and FS0~FS2 setting.
    Best regards,
    Shawn Zheng