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CCS/DRV8312: Can I choose the CBC mode for 2-quadrant operation of BLDC motors?

Sewoong Kim
Prodigy 60 points
Part Number: DRV8312

Tool/software: Code Composer Studio

Hi Motor Applications Team,

Since "OT latching shutdown mode is recommended to prevent the channel with low side FET on stuck in Hi-Z during OC event in CBC mode" is described  in the data sheet(page 13), I selected the OC latching shutdown mode for 2Q operation. but, the DRVs were latched in the Hi-Z  state by the inrush current and  I have to reset the DRVs periodically to restore the DRVs.

 I tried the CBC current limit mode for 2Q operation. In the case DRVs were not latched in the Hi-Z state and overall drive system works well without periodic reset.

 Both of the OC-ADJUST Resistor are 43k ohm..

So, I like to choose CBC mode for 2Q operation, but I want to clearly understand the reason why you recommended OC latching mode instead of CBC.

 1. Does "OC event"  means the over current during short to power and short to ground conditions?
 
 2. Does "low side FET on stuck in Hi-Z"  means FET stays in Hi-Z state, not in turned on state?
   
 3. Is there ways to resolve the problem with the CBC mode?

 4. I think the "OC event and stuck in Hi-Z state" also occurs in the complementary operation and  CBC mode. 
    Even if it happen. is it not a problem in the case?
 

Sincerely

Sewoong KIm.

  • 0
    TI__Guru** 114905 points
    Hi Sewoong,

    1. Does "OC event" means the over current during short to power and short to ground conditions?

    "OC event" means the current is greater than specified by the OC-ADJ resistor plus/minus the 20% tolerance.

    2. Does "low side FET on stuck in Hi-Z" means FET stays in Hi-Z state, not in turned on state?

    Correct. If an OC event occurs, the output that was low will be disabled.

    3. Is there ways to resolve the problem with the CBC mode?

    Yes, do not operate the low side at 100%. Please refer to the third paragraph of page 12.

    It is important to note that if the input to a half bridge is held to a constant value when an over current event
    occurs in CBC, then the associated half bridge will be in a HI-Z state upon the over current event ending. Cycling
    IN_X will allow OUT_X to resume normal operation.

    A small high pulse on the low side FET (50 ns) should be enough to reset the low side.

    4. I think the "OC event and stuck in Hi-Z state" also occurs in the complementary operation and CBC mode.
    Even if it happen. is it not a problem in the case?

    As long as the inputs are operated at less than 100%, complementary operation should not be a problem.
  • 0 in reply to Rick Duncan
    Prodigy 60 points

    Hi Rick,

    Thank you for the reply !

    Best Regards

    Sewoong Kim