DRV8432: Fault Pin behaviour in cycle by cycle mode

Vitali Lach

Part Number: DRV8432

Hello,

I've got a question about "FAULT_N" Pin from DRV8432. When the driver is in the cycle by cycle mode (18.7A, two DRV8432 in parallel mode), we see some fine "Low" peaks on the "FAULT_N" output while that pin remaning "High". Radj=24K. Is that behaviour from "FAULT_N correct?

Best Regards.

Vitali Lach

over 7 years ago

0 James Lockridge19 over 7 years ago

TI__Genius 14487 points

Hello Vitali,

If the FAULT_N pin is pulling low, this indicates that the device detected a fault. If it is happening repeatedly, then the device might be experiencing a an overcurrent condition. Since you have it in cycle-by-cycle mode, the device disables when it detects a fault, then it re-enables for the next cycle. When it re-enables, it sees the fault again and disables again.

The FAULT_N pin and the protection features are described in sections 7.3 and 7.4 in the datasheet.

0 Vitali Lach over 7 years ago in reply to James Lockridge19

Expert 1130 points

Hello James,

thank you very much!

0 Vitali Lach over 7 years ago in reply to Vitali Lach

Expert 1130 points

Hello James,

our customer would like to ask another question about that driver.

Is there any “OC Latch Mode” In the “1PFB” configuration (Mode Pins set as 0 1 0) which could be adjusted by “’OC_adj” resistor?

Best Regards.

Vitali

0 James Lockridge19 over 7 years ago in reply to Vitali Lach

TI__Genius 14487 points

Hello Vitali,

I apologize for my delayed response. The OC_ADJ pin should also set the over current threshold for the latching or cycle-by-cycle OCP in parallel full-bridge mode as well.

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DRV8432: Fault Pin behaviour in cycle by cycle mode