• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 346 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8323: question from layout guide

user021864
Intellectual 2145 points
Part Number: DRV8323

Hi, 

I am checking layout from the guide line and having some problem: 

1. why the width of gate signal needed to be more than 20 mils? what will be the problem if not?

2. what is the mean by route as a differential? 

does that mean the length need to be the same of SLx and SPx?

thank you.

  • 0
    TI__Genius 14487 points
    Hi user021864,

    1. The traces for the gate-drive signals must be able to accommodate 1-2 A. Traces that are 20 mil or larger should be able to accommodate that current. Also, larger traces have lower impedance, so there is less risk for transients from trace parasitics to stress the driver and FETs.

    2. Differential routing means routing the signals for SL and SP so that they are close to one another and they are the same length. The URL below from Altium describes differential routing in greater detail.

    www.altium.com/.../((Differential Pair Routing))_AD