DRV8703-Q1: Review of Protection Functions

Hello Sakai-san,

My responses are in blue.

1. GDF.

Are there the voltage threshold on each to judge error or normal after tDRIVE?

JL: I do not currently have voltage threshold error data available for the GDF feature. The purpose of the GDF is mainly to detect shorts from GHx or GLx to GND, SHx, or VM. Is the customer concerned by a particular condition that makes them ask for this data?

2. OTW .

1) I wonder the temperatre measurement on the chip would be just 1 point & it used for OTW & TSD? If that true, OTW happened, then TSD happened would be reasonable senario?

JL: TSD occurs at higher temperatures than OTW. OTW only indicates that the device is near TSD. If the device heats further, it will shut down.

2) For clear OTW bit, the writing CLR_FLT bit was needed?

JL: The OTW bit should clear when the device temperature reduces.

3. TSD.

Is it possible to clarify the max. value of TSD? Too higher temperature will create other concern such as degradation.

JL: Some of our other gate drive devices specify TSD to 185C. That is my initial guess for an upper limit, but I can investigate further if needed. Since the DRV8703-Q1 is a gate driver, it will likely not have a significant amount of self-heating. This device likely will only experience an overtemperature condition if the ambient temperature or nearby devices exceed 150C.

4. SPI I/F Diagnostic.

The customer is considering the method to realize SPI I/F diagnostic on DRV8703-Q1.

1) ADRS 0x02, LOCK bits will be 011 or 110. They considering to write 000 on this register & read out 0x02 to be all 0. Is it no problem to write 000 on ADRS 0x02 LOCK bits?

JL: There is no problem writing 000 to the LOCK bits. The register map in the datasheet provides the following description to confirm this: “Writing any sequence other than 110b has no effect when unlocked.”

2) Personally, /FAULT pin check => Write 1 to CL_FLT bit => Read ADRS 0x00=all 0. This way would be safer to avoid miss-setting of register. How do you think?

JL: The Fault Status Register is read-only. You will not accidentally set this register. If you clear all the faults before you read the fault register, then you won’t know what fault occurred.

Sakai-san,

When a gate-drive fault occurs, the driver is not truly controlling the MOSFET. The condition that causes a GDF is a short on GHx or GLx causing the gate-drive current to flow into a path other than the FET gate. In this condition, a MOSFET may be stuck in the ON state, and the motor will not be controlled correctly by the INx pins or the current regulation circuitry in the device. Our driver is able to detect this kind of fault condition and disable the motor so it doesn't burn up if the FETs are operating in an uncontrolled way. The detection method looks for the voltage on the gate-drive output to change while sourcing current into the FET gate. The gate charges and discharges like a capacitor, which causes this voltage change. In the case of a short, this voltage will not change.

This kind of failure may be a MOSFET failure or a mechanical failure. If the MOSFET is replaced, or the mechanical path shorting the gate drive output is cleared, then the DRV8703-Q1 will resume normal operation.