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DRV8432: Cycle By Cycle Overcurrent Limit in Single Magnitude mode?

Roman Keller77
Prodigy 10 points

Part Number: DRV8432

Question:

Are there any use restrictions for Cycle By Cycle Overcurrent Limit or Overcurrent Latch when driving single magnitude mode?

Can you explain how the currentsenssing in each halfbridge works to understand what we currently see?

Explanation of the Application:

In one Project we use the dual fullbridge Mode, and the Bridges are completely independent from each other. The PWM is applied Single Magnitude. (Dutycycle aimed 60% ==> A=60% B=0%)

In that application we have the issue that the OC_Latch is shutting down the controller before OC_CBC even started to work.

Now the PWM is applied in Dual Magnitude mode. (Dutycycle aimed 60% ==> A=80 B=20%). This is now Working, but with the higher Switching losses we are closer to the Thermal limit of the System.

Now in another Project the Single Magnitude mode is combinded with the single fullbridge mode:

Here the OC_CBC is not working either, can you explain that.

Regarding to your answer here e2e.ti.com/.../2620113

No OC_Latch is existing in single fullbridge mode. Then we have a Problem because none of the OC functions is working at the moment.

  • 0
    TI__Guru** 114905 points
    Hi Roman,

    Can you provide scope captures of the currents in both projects?
    Also, can you provide a schematic of the connections?

    A latched shut down in CBC mode may be an indication of a short circuit. When selecting CBC mode, there is still a second circuit that can shutdown the outputs. From section 7.3.2.2 of the datasheet:

    In CBC current limiting mode, the detector outputs are monitored by two protection systems. The first protection
    system controls the power stage in order to prevent the output current from further increasing, that is, it performs
    a CBC current-limiting function rather than prematurely shutting down the device. This feature could effectively
    limit the inrush current during motor start-up or transient without damaging the device. During short to power and
    short to ground conditions, the current limit circuitry might not be able to control the current to a proper level, a
    second protection system triggers a latching shutdown, resulting in the related half bridge being set in the highimpedance
    (Hi-Z) state. Current limiting and overcurrent protection are independent for half-bridges A, B, C, and,
    D, respectively.