DRV8305: not getting pwm output

Hi Rashi,

Can you provide some information about your system setup?

1. What is your PVDD voltage?
2. Are you setting the EN_GATE pin high before attempting to apply the PWM input?
3. Is nFAULT low?
4. Are there any fault flags in registers 0x1, 0x2, 0x3, or 0x4?
5. Are you trying to use 1x, 3x, or 6xPWM mode?

Thanks,

Garrett

Hi Garrett,

1) My PVDD Voltage = 12V
2) Yes, giving 5V Enable Signal before providing PWM Inputs
3) Yes nFAULT Pin is Low
4) Only the Fault Bit Register in Address 0x1 is High, the remaining all other values are default (0)
5) Currently using 1 PWM Mode, where I am providing 500Hz 50% Duty Cycle PWM Signal.

Hi Rashi,

Are you testing with the motor connected, or are you directly observing the outputs of the IC? If your motor is hooked up, please disconnect it for now to make debugging easier.

Can you measure your inputs on the INLA/INHB/INLB pins? If all three of those inputs are low, then as per the State Table for 1-PWM mode, all of the gate outputs will be held low.

Thanks,

Garrett

Hi Garrett

Thank you for your kind reply 

Yes we are testing it with the motor disconnected and checking for waveform on GHx and GLx as well as INLA/INHB/INLB also, on MOSFETs output.

There is 1Khz PWM signal on INHA and switching sequence being applied to INLA/INHB/INLB as per figure-8 in the datasheet and a continuous low on INHC. 

period for each signal is about 2ms and each signal overlaps the previous signal by 1ms.

The nFault pin remains low, after reading the SPI status registers the PVDD undervoltage flag remains high even though when we are applying 12V on PVDD.

Thanks

Rashi

Hi Garrett,

There is an update to previous message

We have detected Fault Bit Register in Address 0x1 is High, AVDD undervoltage flag (AVDD_UVLO, bit D5) in register 0x3 and PVDD undervoltage flag (PVDD_UVLO2, bit D10) in register 0x3 is also high. Although we have given 12V on PVDD, the voltage on VReg pin is at 2.89V only. From the data sheet, shouldn't we get 3.3V output from Vreg pin in case of DRV83053? Or do we have to supply 3.3/5V from external source?

Thanks

Rashi

Hi Rashi,

Let's address these faults individually:

1) PVDD_UVLO2

PVDD_UVLO2 is triggered by PVDD falling below 4.4V. Usually I see this fault occur when either the power supply does not supply sufficient current, or the PVDD supply on the board is otherwise constrained. What is the current limit on your power supply? How much capacitance do you have connected to PVDD? Are there any other components restricting the connection of PVDD to the power supply?

2) AVDD_UVLO

AVDD_UVLO is triggered by AVDD falling below 3.7V. This is potentially related to the PVDD dropout, since AVDD is supplied from PVDD. It could also be related to the AVDD regulator itself. How much external capacitance is attached to the AVDD pin? Are there any other external components attached?

3) Vreg Voltage

If you are using the DRV83053, then yes, the VREG pin should be regulating the output closer to 3.3V. How much external load are you placing on VREG? How much external capacitance is connected to the VREG pin?

Thanks,

Garrett

Hi Garrett,

1) we have attached the oscilloscope pins on PVDD input supply voltage and there is no sign of voltage drop recorded on the oscilloscope. That means it is steady 12V supply.

we have connected 4.7uF capacitor from PVDD to ground. Any other component is not restricting the power supply.

2) only  1uF capacitor  attached to AVDD, no other components.

3) 1uF capacitor  attached to Vreg.

my concerns are:

1) nfault pin remains low from start.

2) can we test the circuit without the H-bridge, just to make debugging easy?

Hi Rashi,

All of those components are the datasheet-recommended values, so they seem fine.

1) If nFAULT remains low from the start, the PVDD_UVLO may just be from PVDD rising slower than the device start-up sequence. Before attempting to apply the PWM input, could you write a "1" to the CLR_FLTS bit in register 0x9 to clear the device faults? Then see if any new faults occur when the PWM input starts.

2) Yes, however, this may cause VDS faults, since the gate won't turn on to connect the drain and source

Thanks,

Garrett

Hi Garrett

Thank you for your support.

My problem has been resolved .

I have connected SN1, SN2, SN3 pin for back sensing, which makes AVDD pin to ground .

Please help me with 6-mode input signal, waveform below shows the output in 1-mode and 6-mode

MOSFET output in 1-mode

output in 6-mode

channel-1 is MOSFET output from  phase-A, channel-2 is input to AH and channel-3 is input to AL.

I want to know how to give input in 6-mode.

Thanks

Rashi

Hi Rashi,

I'm not sure I understand the question you're asking here, can you try to clarify?

In 1xPWM mode, a single PWM signal is applied to the INHA pin, and the DRV8305 uses an internally stored commutation pattern to turn on/off the three high side and low side gates based on the state inputs of the INLA, INHB, and INLB pins.

In 6xPWM mode, each high side and low side gate output is controlled directly by its respective input pin (INHx/INLx), so the commutation pattern must be provided by the MCU for each gate.

Thanks,
Garrett

Hi Rashi,

1) Can you read back any fault codes when the motor stops spinning? If the gate drivers are disabled there will likely be an associated fault causing this to happen

2) Is this happening on multiple units, or just one? If it's just one, I would suspect that maybe a manufacturing defect caused a short between some of the pins. If it's happening on multiple units, then the issue is more likely systematic. What is the voltage rating on your capacitors connected to VCPH, CP1H/CP1L, and CP2H/CP2L?

Thanks,
Garrett

Hi Garrett,

1) yes, fault register 3, bit D4 i.e VCP_LSD_UVLO2  fault is detected. I there any way to disable this?

2) Happened on multiple units so we replace peripherals with the new one which resolves the sparks problem. Voltage rating of capacitor on pins VCPH, CP1H/CP1L, and CP2H/CP2L are 25V, 50V and 50V respectively.

Thanks

Rashi