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DRV8353: SPI daisy chaining?

Stefan Skoog6
Prodigy 10 points
Part Number: DRV8353
Other Parts Discussed in Thread: SN74LV138A

Hi,

I'm looking at driving multiple DRV835xS with a C2000 Delfino (up to 24 ch PWM available --> up to 8 DRV835xS). The SPI function in DRV835xS is really great to minimize tons of hard-wired signals for configuration, calibration and status read. I've scrutinized the available datasheet dated this August 2018, but I can't find anything that supports that SPI can be daisy-chained with several DRV835xS's. Quite the opposite, datasheet states that any SPI data over 16 bits clocked in will be rejected. 

My µC pins are already running short (especially during development phase where a LaunchPad will be used). Using 8 SPI individual data channels is out of the question. Using 8 chip selects and sharing SDO, SDI, SCK could work, but it slows down the communication process if I have to bit-bang the CS's instead of leaving that to the C2000 hardware module.

Any ideas?

Thanks for offering really exciting products by the way!

- Stefan

  • 0
    TI__Guru** 114905 points
    Hi Stefan,

    The DRV835x devices do not support daisy chaining. As you mentioned, you can share the SDO, SDI, and SCLK.

    If you are GPIO limited, please consider adding an external decoder/demultiplexer (like the SN74LV138A ), an I/O expander with a SPI interface, changing your uc to one with more GPIOs.