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DRV10983-Q1: Is the FG pin the open drain?

downey KIM
Intellectual 600 points
Part Number: DRV10983-Q1


Hello TI team.

The recommended operating conditions for the FG pin in the DRV10983-Q1 data sheet are 3.6V maximum.

The MCU Vcc of the system is 5V.

Can i design 5V pullup on the FG pin? or should i design 3.3V pullup?

Is the FG pin the open drain?

Thanks.

  • 0
    TI__Mastermind 18900 points
    Hey Downey KIM,

    Yes, the FG is an open drain output. However, the internal FET is rated for 3.3V (technically, 3.6V for normal operation and 4V absolute max).

    Please design a 3.3V pull up or use the V3P3D pin on our device. If you need to use the signal with the MCU (that I assume is 5V logic), take a look at our logic translators.

    Best,
    -Cole
  • 0 in reply to Cole Macias
    Intellectual 600 points

    Hi cole.

    One more question.

    MCU(Vcc 5V) do control PWM speed of DRV10983-Q1. The voltage was divided by the resistors Due to the difference in operating voltage.

    The internal LDO of the DRV10983-Q1 does not work if a resistor divider is inserted. If R17 and R20 are removed, the internal LDO operates normally.

    An internal 5V step-down regulator was applied a resistor option.

    Even with the inductor option applied, the 3.3V LDO will not work.

    I ask for your advice.

    Thanks.

  • 0 in reply to downey KIM
    TI__Mastermind 18900 points

    Hey Downey Kim,

    I could see two possibilities. One is that there is some sort of loading on VREG or one of the LDO's that is causing the voltage to drop out. Another is that you are using sleep mode part and the device is not successfully waking up.

    Loading on VREG or LDOs:

    Can you confirm that the VREG and V3P3 are not being loaded passed their IREG_MAX (100mA when using the inductor and 5mA for using the resistor) and I3P3_MAX specs (20ma when using the inductor)?

    You mentioned that neither the Inductor (buck mode) nor the resistor (linear mode) helped the situation. This means the system would have to be pulling >20mA on V3P3 or >100mA on VREG. This is probably less likely.

    Sleep Mode:

    Since this looks like it is a custom board, can you confirm that you have a DRV10983SQ1 and not a DRV10983Q1? If you are using the DRV10983Q1 then this is a sleep mode part. The LDO's and VREG turn off when in sleep mode. This means any load attached to them will not be powered. If the MCU is powered by the DRV10983-Q1 and not externally, have you checked the PWM_VSP signal or power rails on the MCU?

    If the MCU is powered then we need to ensure the PWM is meeting the conditions to exit the device from sleep mode. Generally speaking, the "Sleep or Standby Condition" in the datasheet shows that the SPEED pin must be high (V>VDIG_IH = 2.2V) for tEX_SL_SB (2µs) to exit sleep mode in PWM mode.

    Probe PWM_VSP and see if the waveform meets this requirement.

    Best,

    -Cole