DRV11873: loss of lock

If the goal of finding a revised version of DRV11873 is to see if the revised version doesnt have the false lock rotor condition, unfortunately there isn't a version of the DRV11873 that doesnt have this false lock rotor condition.

However, if you'd like, I'd like to try to understand your application and see if there is a workaround.

Description of the false locked rotor condition:

-If the FG signal closely matches the 101.6Hz internal sampling clock, and the FG signal is sampled as a static value for approximately 305 clocks of an internal sampling clock, the internal logic falsely signals that the rotor is locked.

Which of the following three matches your case?:

1) Target Motor Speed is Fixed Inside the False Detection Range of 101.6 Hz ±30%

2) Target Motor Speed is Fixed Outside the False Detection Range of 101.6 Hz ±30%

3) Target Motor Speed is Variable With FG inside the False Detect Window

What I'm confused about is that you mention " DRV11873 consistently enters into a false locked rotor state beyond a certain motor speed". However, there shouldn't be a speed threshold above which the false lock detect triggers. Rather, false lock detect only happens if the speed correlates with an fg freq that is close to a multiple of 101.6Hz internal sampling clock, and it has to be detected for 305 samples, which means you have to stay at that speed for 305 samples/101.6Hz = 3 full seconds. You should be able to go past any speeds that could cause a false lock detect. Can you clarify this.

Another option our customers decide to do is to switch to the DRV10974 which provides similar performance, and doesnt have this problem.

 

Hi!

Many thanks for your reply. I will examine the DRV10974 as an alternative.

The motor speed threshold I mentioned is not quite a threshold as you have stated - I have since realised that it is due to the rate of acceleration of the motor up to the target speed. Our application dictates a high inertial load on the motor which leads to the acceleration declining slowly as the target speed is approached. As the motor spins up, it quickly goes through a few multiples of the false detection range, however beyond a certain speed the acceleration drops low enough for the motor to spend a period greater than 305 samples in a multiple of the false detection range on its way up to the target speed. I hope that makes sense!

The final target speed is not variable and is not within the false detection range.

I hope that explains the issue better and I look forward to your reply!

Hey Youssef,

I understand your point about speed acceleration decreasing slowly as target speed is approached.

Here is a quick suggestion:
-Try changing the Vcc/pwm duty to something much higher such that at your target speed, the acceleration is faster and the motor doesn't spend a period greater than 305 samples in a multiple of the false detection range.
-Modulate the PWM input between 2 duty cycles 1% to 2% apart. Do this every 1 to 1.5 seconds to prevent the FG frequency matching the internal sampling frequency. The result is an average speed of the two PWM duty cycles". For example, alternate between pwm duty 95% and 97% every 1 to 1.5 seconds. This will give you a speed associated with average 96% duty cycle.
-Basically you are taking advantage of the fact that the fg pin doesnt represent the average speed, but rather the immediate speed/commutation frequency, so if you alternate the pwm duty cycle such that you have an average speed, you should potentially avoid the false detection range for too long. The higher Vcc suggested in the first bullet will also allow the motor to shift speeds faster and have less chance of spending a period greater than 305 samples in a multiple of the false detection range.

Let me know if this works.

Sincerely,
Sanmesh U.

Hey Youssef,

Were you able to solve your problem?

Sincerely,
Sanmesh U.

Hi Sanmesh,

Thank you for your suggestions, I very much appreciate your support with this!

Firstly, I was able to try out the DRV10974 using the EVM board. Unfortunately, I was not able to achieve the desired performance after attempting to tune the driver using the provided tuning guide by changing the resistors on the RMP, CS and ADV pins. The main problem I had was achieving reliable motor starting, even with the lowest acceleration setting and the appropriate CS setting. The open loop acceleration always seems to fail. I also faced this problem when testing the 10975/83. In contrast, the reason I'm interested in the DRV11873 in particular is the starting reliability - it never has any trouble starting the motor instantly.

Unfortunately, in this application a higher Vcc is not possible to achieve due to power supply constraints. Additionally, the current Vcc setting is already at the maximum allowable supply voltage the DRV11873 can handle (18v). I have attempted the PWM modulation technique you suggested and was not able to avoid the false-lock. I believe it is to do again with the high inertial load on the motor, meaning it cannot respond to changes in the control signal fast enough to modulate around the false-lock range without triggering it.

I'm wondering if there is a mechanism you are aware of by which the FG output  can be interfered with or masked in such a way as to essentially override the signal and disable the lock detection feature?

Please let me know your thoughts on these results so far.

Regards,

Youssef