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DRV8305-Q1: Power-Up Sequence

hideyuki sakai
Mastermind 6250 points
Part Number: DRV8305-Q1

Dear, Sir.

My customer is evaluating DRV83055QQ(Integrated 5V LDO) version.

Now, they are asking about the Power-Up Sequnce definition.

1. Figure 15 shows the definition. PVDD_UVLO2 is defined min. 4.4V/max. 4.7V @ rising.

    How about the Logic Threshold? Digital I/O VIH = min. 2V/max. 5V?

2. Thecustomer is connected with 5V MCU via SPI. I think internal logic is operating with

    3.3V. Is it no problmem to connect DRV83055QQ with 5V MCU? It has 5V tolerant?

Sorry again & again, but please give your advice.

Best Regards,

H. Sakai

   

   

  • 0
    TI__Intellectual 1345 points
    Hi Sakai-San, no sorry ever needed on e2e forums !

    Yes, 5V internal (DRV83055QPHPRQ1) LDO version is intended for 5V MCU.
    The reason why the customer is able to communicate through SPI even at 3.3V is that the SPI block is powered through VREG directly (not through PVDD). So, as the regulator is powering up , SPI communication becomes possible but driver operation is not possible until PVDD_UVLO2 is reached.

    This is described in the datasheet as below :
    "7.3.7 VREG: Voltage Regulator Output
    The DRV8305-Q1 integrates a 50-mA, LDO voltage regulator (VREG) that is dedicated for driving external loads
    such as an MCU directly. The VREG regulator also supplies the reference for the SDO output of the SPI bus and
    the voltage reference for the amplifier output bias"
  • 0 in reply to Anuj Narain
    Mastermind 6250 points

    Dear, Anuj-san. 

    My question about VREG has been cleared. Thank you so much for your teaching. 

    The other side, "Logic Threshold" on Figure 15, Power-Up Sequence is still not cleared. 

    Please give your advice on this remaining question. 

    Best Regards, 

    H. Sakai

  • 0 in reply to hideyuki sakai
    TI__Intellectual 1345 points

    Hi Sakai-San, 

    The logic threshold indicates that the DVDD voltage regulator has reached its nominal voltage (nominal voltage =3.3V but can be active at a slightly lower voltage) 

  • 0 in reply to Anuj Narain
    TI__Intellectual 1345 points
    Hi Sakai-San,
    Do you have any additional questions or is this resolved ?
  • 0 in reply to Anuj Narain
    Mastermind 6250 points

    Dear, Anuj-san. 

    Thank you so much for your detail explanation. 

    The Logic Threshold is defined based on PVDD. According your explanation, 

    The PVDD voltage would be DVDD nominal = 3.3V + DVDD LDO Dropout voltage. 

    Is it possible to clarify the DVDD LDO Dropout voltage? 

    Or Internal VREG become operational at PVDD = 4.3V. It is defined by datasheet. 

    The PVDD voltage would be referred this voltage?

    You don't need to assure that, but we need a kind of criterion on the definition

    by datasheet. 

    PS)

    the customer is used DRV83055Q(internal 5V VREG version). 

    Best Regards, 

    H. Sakai

  • 0 in reply to hideyuki sakai
    TI__Intellectual 1345 points
    Hi Sakai-San,
    a) for internal 5V VREG version, the condition for SPI communication is PVDD > PVDD_UVLO2 . There is no dependence on DVDD
    b) for external VREF version , the condition for SPI communication is PVDD> ~3.3V

    Since the customer is using (a) the DVDD voltage and DVDD LDO dropout does not matter. It is very small anyways.
  • 0 in reply to Anuj Narain
    Mastermind 6250 points

    Dear, Anuj-san. 

    Thank you so much for your reply & information. 

    Question regarding SPI has been cleared, already. 

    I would like to know the PVDD voltage at "Logic Threshold" on 5V VREG version. 

    The datasheet defines that digital logic will become active, VREG will enable. 

    It should be over 3.3V(DVDD output) because PVDD should be over DVDD. 

    I am expecting your clarification about PVDD voltage at "Logic Threshold" on 5V VREG version. 

    Best Regards, 

    H. Sakai

  • 0 in reply to hideyuki sakai
    TI__Intellectual 1345 points

    Hi Sakai-San,

    For 5V VREG version, Logic Threshold will be over PVDD=3.3V

    For 3.3V VREG version, Logic Threshold will be over PVDD=3.3V

  • 0 in reply to Anuj Narain
    Mastermind 6250 points
    Dear, Anuj-san.

    Thank you for your reply.
    VREG output between PVDD=4.4 to 5.3V is defined on datasheet.
    It means that VREG has started up already.
    PVDD = 4.3V is defined as VREG operational voltage on datasheet.
    I guess "VREG will enable" equal in this voltage.
    I wonder my guess is wrong?

    Best Regards,
    H. Sakai
  • 0 in reply to hideyuki sakai
    TI__Intellectual 1345 points
    Hi Sakai-San,
    Your guess is correct. VREG will only be enabled at PVDD=4.3V