• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 29 subscribers
  • Views 1172 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8702-Q1: VREF pins

Federico Silva
Intellectual 795 points
Part Number: DRV8702-Q1
Other Parts Discussed in Thread: DRV8703-Q1

Hi,

I've designed a board with this gate driver and the IPG20N10S4L-22, to be driven by independent PWM. However, as soon as it turns on, the nFault triggers, even with nothing on the inputs.

Can you spot any problem with the board?

Thanks,

Federico

  • 0
    TI__Expert 8985 points

    Hi Federico,

    When you turn it on, are you already turning on the GHx/GLx signals?

    Can you please validate on your end if any of these specific faults are triggering by measuring VM and VCP voltages?

    1. UVLO (Vm < 5.45 V)

    2. CPUV (Vcp < Vm + 1.5V)

    If its not any of those two, then we can check WDFLT among other faults.

  • 0 in reply to Hector Hernandez Luque
    Intellectual 795 points

    Hi Hector,

    Thanks for the answer. I checked those voltages and they seem to be all right. VM is 30 V and VCP is 40 V. Here is a screen capture of the oscilloscope:

    C1=VCP; C2=VM; C3=GL2; C4=GH2

    I think the watchdog timer only applies to DRV8703-Q1, not the 02.

    I did notice however that there are little glitches on the gates of the transistors, even though both inputs are 0.

    Do you notice anything wrong in my schematic or something else?

    Regards,

    Federico

  • 0 in reply to Federico Silva
    TI__Expert 8985 points

    Hi Federico,

    A couple of important pins I did not notice were disconnected: SP, SN, and VREF. Now, you are not utilizing the SP or SN for your board, but, in the case, they need to be connected to GND. Additionally, VREF pin should be connected to a voltage higher than 0 V. Traditionally, VREF is AVDD.

    Please, update me once you make these changes to know if the board is functional.

  • 0 in reply to Hector Hernandez Luque
    Intellectual 795 points

    Hi,

    But the datasheet says that in case of independent PWM driving, current regulation is disabled. What does it change then?

    Thanks,

    Federico

  • 0 in reply to Federico Silva
    TI__Expert 8985 points

    Hola Federico,

    On section 7.3.4 Current Regulation, the last sentence states, "If the current regulation feature is not needed,it can be disabled by tying the VREF pin directly to the AVDD pin."

    I stated to you that it should be tied to a voltage higher than 0 V. It is actually required to be tied directly to AVDD.

    In section 7.3.10 Overcurrent VDS Monitor, the last sentence in it states, "Ensure that the SP pin is always connected to the source of the low-side FET of half-bridge1, even when the sense amplifier is not used."

    I stated to you that SP should be tied to ground. It is actually required to be tied to the source of the low side FET for low side Vds(ocp) monitoring of half bridge 1 (see Figure 41 for a internal device module view).

    As for SN pin, we recommend it is tied to ground to make sure SP-SN is not > 1 V (OCP fault).

  • 0 in reply to Hector Hernandez Luque
    Intellectual 795 points
    Hola Hector,

    thanks for the info. I got confused when it says that in independent PWM driving, current regulation/chopping was disabled; I assumed the whole protection was disabled.

    Federico