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DRV8860: Daisy chain limitations and timing

Part Number: DRV8860

I am looking to daisy chain some DRV8860 chips. I have a few questions...

1. Is there a maximum number you can daisy chain?

2. For the timing constraints in section 7.6, the latch to clk time (th) is 1 uS. Is that the delay I need to give it before the clk signal is generated? 

3. For the CLK high and low time, it says a minimum of 2.5 uS. Does that mean I can go no slower than 400 Khz on the clk?

4. Are there any timing constraints when daisy chaining?

  • Hi Andrew,

    1. Is there a maximum number you can daisy chain?

    There is no maximum number.

    2. For the timing constraints in section 7.6, the latch to clk time (th) is 1 uS. Is that the delay I need to give it before the clk signal is generated?

    Yes, that is correct.


    3. For the CLK high and low time, it says a minimum of 2.5 uS. Does that mean I can go no slower than 400 Khz on the clk?

    No, that means the CLK frequency can be no faster than 200kHz. The CLK high and low time must be a minimum (greater than) of 2.5us.

    4. Are there any timing constraints when daisy chaining?

    As long as the timing in the datasheet is met, the devices should function.

    The DOUT to DIN timing could be affected by the pullup value and parasitic capacitance on the pins and traces.