This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8353: Gate drivers dying

Part Number: DRV8353

Hi.

I'm having some trouble with the gate drivers on the DRV8353 failing after minimal use.  Oddly, this is happening during bring-up with no-load or a small resistive load, reasonable voltages (14-24V); I haven't gotten anywhere close to the operating conditions.

I power up the bridge (slowly, by dialing up my bench supply from zero) and apply the logic reference voltage.  Pull up the enable line, then manually toggle the INxy pins to ensure the bridge is being driven.  After a few transitions, the FAULT line will assert and one of the Gxy will no longer be functioning (will always trigger the FAULT when I try to turn it on).  Looking at the Gxy lines, the 'damaged' one will show an erroneous voltage in the off state (e.g. GLy will be > 0V when off) and the impedance to ground when unpowered will be much lower than the other channels and much lower than an undamaged board.  

  • I have isolated the H-bridge gates from the driver and found them all to be in good shape.  I've damaged 3 boards now with two of the failures on low-side drivers and one on high-side.
  • I have de-pop'd all but a single FET in each leg of the bridge, and seen the same effect.  FETs are Toshiba TPH2R608NH,L1Q.
  • Part is configured as 6 PWM, max drive, using the internal buck to create 12V which powers VM.
  • The gate drive runs are long, but the GHy are reference to SHy, while the low side are ground (~SyP) referenced keeping the loop-area/inductance small.
  • Gates are isolated each with a 1ohm resistor, and individually protected with a small TVS (theoretically providing some protection to the gate drivers as well)

I based the layout on the reference design and can't see any notable differences aside from the much larger bridge.  

Any thoughts on what might be causing this would be greatly appreciated.

-Chris

 

  • Chris,

    What is your expected GATE signal rise and fall time? Max IDRIVE can damage the DRV given too much inductance in the gate line or gate ringing. What I suspect is happening is that the 1 ohm is not enough to slow down the massive gate current and the driver is getting damaged. At 18nC per FET, four FETs in parallel, you're switching 72nC per gate line. Assuming a quick turn on of 200nS, this would need IDRIVE of 72nC/200nS or 360mA. The 1 ohm isn't limiting much current. I would suggest using an IDRIVE closer to 360mA and checking if the damage still occurs.

    Regards,

    -Adam
  • Thanks for getting back so fast, Adam! I'll give that a shot by taking IDRIVE to DVDD via a 75k. I had intended to turn them on a lot faster as the contribution to heating from switching [using: 0.5*Vbridge*Ibridge*(Ton+Toff)*Fsw to estimate the switching contribution] gets pretty high when I'm switching at frequencies above the acoustic range. However, I'd be happy to get something that's working at a lower Fsw and then work on optimization.

    Any thoughts on sizing the gate resistors vs adjusting the gate drive?
  • Chris,

    I would definitely get the motor spinning and prevent damage first, then tune up the IDRIVE slowly once you're mostly happy.

    Adjusting the gate resistors is another way to do it but I figured it was easier to first adjust the IDRIVE without changing all 16 gate resistors.

    Since we have smart gate drive, the gate resistors are mostly for balancing between the 4 FETs per gate line.

    Regards,

    -Adam
  • We're making progress! A combination of gate resistance and the reduced IDRIVE and I haven't taken out a gate driver in several hours now. Even wired it up to an old starter solenoid and we held our own. I'm seem to be losing my on-board buck regulator now but I'll chase that down in another thread (if needed). Thanks for the help!
  • Chris,

    Glad to hear!

    Regards,

    -Adam