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DRV8860: DRV8860 output crosstalk

Don Foong
Expert 4100 points
Part Number: DRV8860

Hi Team,

One of our customer has done some test with our DRV8860 on their prototype board (follow EVM circuit). DRV8860 is design to drive the valve. They have observed channel crosstalk when driving in one channel . In the below waveform, one channel is PWM switching, an adjacent channel is connected to a valve but in off state.

Can you help to comments what could possible lead to the 'dip' on the adjacent channel and any remedy we could try ?

Look forward to your feedback. Thanks in advance.

  • 0
    TI__Guru 56650 points
    Don,

    I didn't know the root cause yet and will try to test it on Monday. On your side,
    a. order an EVM to speed up debugging process
    b. The issue is happened at PWM Channel's falling edge. Different channels share the same ground. Each channel's gate voltage reference to same ground. At PWM channel's falling edge, the ground current is reduced from PWM FET to common ground. The ground trace voltage is changed the polarity to "Ground "+" and FET source" -". If the ground parasitic inductance is high and this ground voltage jump may affect other channels.
    So, please help me check the IC ground connection between VM local ceramic capacitor ground and IC ground on their layout.
  • 0 in reply to Wang5577
    TI__Expert 4100 points

    Hi Wang Li,

    Thanks for the feedback.

    I have requested one evm for verification at my end. I will try to find out more on customer layout on IC ground connection between VM local ceramic cap, and get back.

  • 0 in reply to Don Foong
    TI__Guru 56650 points
    Don,

    The EVM that I can find has a trouble to communicate with the GUI. I will order an DRV8860EVM to test it.
  • 0 in reply to Wang5577
    TI__Expert 4100 points

    Hi Wang Li,

    Noted, thanks for the feedback.

    Customer has shared the layout as below, they have tried to follow the EVM layout and uses 10uF + 0.1uF for the filter cap. I have also arranged one evm for customer to verify if it has similar issue.

  • 0 in reply to Don Foong
    TI__Guru 56650 points
    Don,

    Thank you for your update. The layout near DRV8860 looks good.

    Would you measure the VM voltage waveform to see if it has same drop as the output? I have to take back my comment before. Ch1 is falling edge is low side FET current rising edge. So, the current is pulled out from input source. If the input source is not strong, we could see the input voltage drop which reflects to all output voltage.
  • 0 in reply to Wang5577
    TI__Expert 4100 points

    Hi Wang Li,

    I have tested the evm with resistive load, no cross talk found. 

    Can we discuss this thread by email ? If ok, kindly send me your email contact to don.foong@ti.com. Thanks.

    Regards,

    Don