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DRV8872: DRV8872 nFault leakage

Barry W
Intellectual 890 points
Part Number: DRV8872

My design pulls nFault to 2.5V through a 10kΩ resistor.

When there is no fault, the voltage at nFault is only 1.7V.  This implies 80µA leakage.  The spec says 1µA max at 3.3V.

I can see nFault fall to 0v when the input voltage falls below 6.3V, so it appears to be functional.

Is it possible the leakage is that much higher at 2.5V?

Should I be using a lower resistance pull up?  The data-sheet has not recommendation.  The EVM uses 10kΩ, but it pulls up to 5V.

  • 0
    TI__Guru** 114905 points
    Hi Barry,

    The leakage should be <1uA as stated in the datasheet.

    Is it possible there is a another path to ground on the nFAULT connection?
    Is nFAULT connected to a GPIO for monitoring? If yes, does it have a pulldown enabled?
  • 0 in reply to Rick Duncan
    Intellectual 890 points

    Thank you for the response.

    The nFault is connected to an FPGA pin configured as an input.  I tried enabling the internal pull up on the IO pin and it made no difference to the signal level.

    I also measured the resistor (10k).  I watched the pin on a scope to make sure it was not oscillating.  I saw it drop when VIn fell below 6.3V.

    I appreciate any other ideas.  Strange issues like this can be a leading indicator of a larger problem. 

  • 0 in reply to Barry W
    TI__Guru** 114905 points

    Hi Barry,

    I have not been able to duplicate your findings, but will continue next week. There is no apparent reason for this behavior.

    While waiting, is it possible to disconnect the FPGA pin from the nFAULT circuit and re-measure?

  • 0 in reply to Rick Duncan
    Intellectual 890 points

    The only way would be to cut the trace or possibly lift the pin.

    You can see the trace travel around the hole in the board from the DRV8872 to the FPGA pin.  That is the pull up resistor just below.

    You can also see the control signal running from the same bank on the FPGA to the DRV8872.

    (This bitmap render of the traces is pretty "crunchy" and they look like they touch.  You'll have to trust that the gerbers are fine.)

    Thanks again for considering my issue.  I have now tested this same behavior on two different boards, both pulled to 2.5V.

  • 0 in reply to Barry W
    TI__Guru** 114905 points
    Hi Barry,

    Understood. I would not recommend cutting the trace. Lifting the pin and wiring a pullup on the pin may be an option, but you will have to make that call. It appears your PCB is much more complicated.

    What is the supply voltage of the FPGA? What is the VOH of the FPGA IO pin?
  • 0 in reply to Rick Duncan
    Intellectual 890 points
    That I/O bank of the FPGA uses the same 2.5V supply. You would like to have 2+ volts.

    I may try lifting the pin and attaching a new resistor, but it will be a few days until I can make that happen.

    Thanks again for the support.
  • 0 in reply to Barry W
    TI__Guru** 114905 points
    Hi Barry,

    Sorry for the delay. I modified the DRV8872EVM to remove the nFAULT diode and 10k pullup to 5V.
    I then connected a 10k pullup to 2.5V.

    The device acted as intended. The voltage on nFAULT was 2.5V. As the VM voltage dropped below the UVLO, the nFAULT dropped to 7.5mV.

    Please try on your end when you get a chance.
  • 0 in reply to Rick Duncan
    Intellectual 890 points
    Thank you Rick for the prompt testing. I have not been able to do update my system yet.

    You have proven it is not the driver. We will continue to look for other causes.
  • 0 in reply to Barry W
    TI__Guru** 114905 points
    Hi Barry,

    You are welcome. Please keep us posted on what you find.