Hi team,
When logic inputs(e.g. 3.3V) from MCU are high with VM=0V, is there a large current leak pass or not?
Thanks in advance.
S.Sawamoto
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Hi team,
When logic inputs(e.g. 3.3V) from MCU are high with VM=0V, is there a large current leak pass or not?
Thanks in advance.
S.Sawamoto
For each digital pin when the respective digital pin's voltage is equal to 3.3V:
AIN1 = 32 mA
AIN2 = 32 mA
BIN1 = 32 mA
BIN2 = 32 mA
nSLEEP = 0 mA
Thanks Hector,
Let me confirm just in case.
It can be estimated the 32mA flows through the internal high-side ESD diode with 100ohm impedance, is it correct?
Does the nSLEEP have a different input ESD structure from xIN?
Regards,
S.Sawamoto
Hi Shinya,
For both questions: I do not have a definite answer at this time. I will verify internally and get back to you with an official response.
Hi Shinya,
I had additional circuitry on those pins I measured the current on. I redid the testing after removing that circuitry and I am confirming the results and internal pin structure with my team. Expect a response in the next couple of days.
Hi Shinya,
I have reviewed the updated results with my team. There is no internal ESD leakage path.
New results.
AIN1 = 0 mA
AIN2 = 0 mA
BIN1 = 0 mA
BIN2 = 0 mA
nSLEEP = 0 mA
My previous results had the MCU connected to the digital pins where I supplied the 3V3 voltage and VM had a 3V3 LDO connected to it. I removed the MCU connections and the LDO to isolate the testing directly to the driver.
Hi Hector,
Thank you so much for your dedicated support work!
Regards,
S.Sawamoto
Hi Shinya,
Further clarification, as I measured my data in mA instead of uA:
AIN1 = 21.45 uA
AIN2 = 20.91 uA
BIN1 = 20.98 uA
BIN2 = 20.76 uA
nSLEEP = 06.23 uA