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DRV8412: DRV8412 drive capacity and heatsink for DRV8432

Part Number: DRV8412
Other Parts Discussed in Thread: DRV832X

I am planning to use DRV8412 to drive the 12A TEC output stage. Two DRV8412 chips will be used in parallel mode. Would that be good enough for 12A operation?

The top heatsink version DRV8432 since to handle higher current, but I find it difficult to install the heatsink and hard to debug as the chip is under the heatsink.

This chip has been around for long time. Is there a newer replacement for this chip?

One of the feature I want on this chip is 100% duty cycle operation as it will generate a refresh pulse to maintain the boost voltage. If there is newer chip can support 100% duty cycle, I would like to consider.

Thanks,

-Marcos

  • Hi Marcos,

    Can you please specify any motor drive features your design requires, along with operation voltage, current and any other design requirements we must be aware of? We might be able to recommend an alternative.

  • Hi Marcos,

    It is not recommended to connect two DRV8412 in parallel. There could be unexpected consequences when doing so.

    Assuming you are operating at high frequencies, the DRV8432 is preferred choice. The DRV8432 can operate up to 500kHz.

    Unfortunately, the DRV8432 does not allow 100% duty cycle. A minimum of 50ns is needed to recharge the bootstrap capacitor each PWM cycle. When attempting to operate at 100% duty cycle, the PWM frequency can be set to 20kHz. Recharging the bootstrap capacitor works out to be .1% off time, or 99.9% duty cycle.

    If you can afford lower switching frequencies (<200kHz) and some variation in the output pulse widths versus the input pulse widths, the DRV832x and DRV835x (3 phase BLDC drivers) with external FETs may be an option. These devices allow you to reduce the RDSon much further.

  • Both DRV8412 and DRV8432 has Bootstrap Capacitor Undervoltage Protection, see section 7.3.2.1  on datasheet, which will automatically generate a short low pulses to recharge the PWM even at 100% duty cycle.

    Since each output has its own output inductor, what is the problem of connecting them in parallel after the inductor? 

    Please elaborate on the potential risk and reference to the section of the datasheet for the concern,

    Thanks,

    -Marcos

  • Hi Marcos,

    When operating two devices in parallel mode (cycle by cycle), there are unknowns as this configuration has not been evaluated.

    One unknown scenario is the OC_ADJ variation (up to 20%) across devices. One device may shut off sooner than the other due to the 20% device to device variation in OC threshold. This could lead to extra heat in the device that remains on, leading to thermal shutdown of the device that remains on.

    This is described in section 7.3.2.2.