Thermal Management design for MOSFET

Jnaneswar Kandula

Other Parts Discussed in Thread: TIDA-010056, CSD19536KTT, CSD17581Q5A

I am working on thermal management design for MOSFET. My MOSFET package is TO-Leadless. I wanted to find the rate of heat transfer from the MOSFET and also need no.of Thermal vias for my component.

I have taken IPT020N10N3 MOSFET and BERGQUIST SIL PAD TSP K1300 for my reference. could anyone can help with these calculations?

over 5 years ago

0 Don Dapkus over 5 years ago

TI__Guru**** 189401 points

Hi, Jnaneswar,

I suggest you check with the MOSFET manufacturer for their recommendations or Berquist for theirs on Silpad.

I don’t believe we have any documents that discuss this.

Hope that gives you some direction to pursue.

0 Jnaneswar Kandula over 5 years ago in reply to Don Dapkus

Prodigy 160 points

I need to know the calculation part which involved in heat transfer for TO-Leadless package. so that i can design my heat sink according to these calculations.

0 Don Dapkus over 5 years ago in reply to Jnaneswar Kandula

TI__Guru**** 189401 points

Hi, Jnaneswar,

Since you are not asking about a TI part, we are unable to help you. I suggest you contact the other manufacturers for help with your question.

0 Jnaneswar Kandula over 5 years ago in reply to Don Dapkus

Prodigy 160 points

Can you give the thermal design calculations for CSD19536KTTT Power mosfet?

0 Don Dapkus over 5 years ago in reply to Jnaneswar Kandula

TI__Guru**** 189401 points

Hi, Jnaneswar, I have asked my colleague who supports that device to comment on this thread. It may be a few days until he responds due to the holidays.

0 John Wallace1 over 5 years ago in reply to Don Dapkus

TI__Mastermind 38330 points

Hi Jnaneswar,

Thanks for your interest in TI MOSFETs. You can start with the the blogs below to get a better understanding of how TI specs thermal impedance for our FETs. The CSD19536KTT is a D2PAK which is similar to the PG-HSOF-8-1 package from Infineon. For this particular package, the thermal impedance from junction to the top case is typically 30C/W. You can find multiple design examples in the Design & development tab in the CSD19536KTT product folder on TI.com. TIDA-010056 shows thermal via placement. You can download gerbers and CAD files for this PCB design on TI.com. I do not have detailed thermal design calculations as this is very dependent on the PCB design and layout.

Understanding MOSFET data sheets, part 6 – thermal impedance

It’ s been a while since posting entries 1 through 5 in this series , but I find myself still fielding several questions about FET datasheets, particularly those parameters found in the thermal information…

By Brett Barr1 over 9 years ago in Technical articles > Power management

How to choose the right power MOSFET or power block package for your application

Other Parts Discussed in Post: CSD17581Q5A When starting a new design, engineers are often overwhelmed by the number of package options for power metal-oxide semiconductor field-effect transistors ( MOSFET…

By John Wallace1 over 5 years ago in Technical articles > Power management

0 Jnaneswar Kandula over 5 years ago in reply to John Wallace1

Prodigy 160 points

Hi John,

Thanks for your valuable information. I wanted to know while designing the heat sink for the Power MOSFET, Is it violable of having 160 no. of thermal vias in 80mm^2 copper soldering area which is located at the bottom side of MOSFET?

Regards,

Jnaneswar

0 John Wallace1 over 5 years ago in reply to Jnaneswar Kandula

TI__Mastermind 38330 points

Hi Jnaneswar,

Happy New Year and thanks again for your interest in TI FETs. I will consult with a colleague on this question. To be sure I understand this correctly, are you asking you can place 160 vias in 80 square mm on your PCB in the thermal pad on the backside of the package? Please confirm. To me, this sounds excessive but I will run it by our SMT experts as soon as you confirm.

0 John Wallace1 over 5 years ago in reply to John Wallace1

TI__Mastermind 38330 points

Hi Jnaneswar,

I have contacted my colleagues to get better recommendations on thermal via placement and spacing for the D2PAK package. I have also found the following application notes which you may find useful:

0 John Wallace1 over 5 years ago in reply to John Wallace1

TI__Mastermind 38330 points

Hi Jnaneswar,

I checked with my colleague. The standard JEDEC via pitch is 1.2 mm. I also took a closer look at TIDA-010056 PCB layout. The vias are spaced 1.36mm apart and there are 30 vias total (6 x 5 array) in the thermal pad area of the D2PAK package.

0 Jnaneswar Kandula over 5 years ago in reply to John Wallace1

Prodigy 160 points

yes i wanted to make 160 vias on my PCB in the thermal pad on the backside of the package. Can you suggest anyother alternative to reduce my thermal loss?

0 Lakshminarayana over 5 years ago in reply to Jnaneswar Kandula

Genius 3790 points

Hi,

I hope this will help:

Thank you.

0 John Wallace1 over 5 years ago in reply to Lakshminarayana

TI__Mastermind 38330 points

Hi Jnaneswar,

The blogs included in the previous response look very useful. From a FET standpoint, the only other suggestion is to consider paralleling MOSFETs to reduce the dissipation and spread it over more than one device and greater surface area. I am going to close this thread. Please feel free to respond if you have any additional questions.

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Thermal Management design for MOSFET