DRV8885: at VM=0V, leakage current from control pin to VM.

Hi Muk,

1. At VM=0V and control pins (nSLEEP, Enable, STEP, DIR ) = 3.3V, Does the device have any issue or concern?

There are no concerns, only power loss. There will be some current flow through the internal pulldown resistors.

2. At the above conditions, Is there any leakage current to VM pin(VM=0V)?

       Logic inputs have only low side diode and Pulldown resister(100k) in the datasheet, I think, no leakage current to VM. Is it correct?

Correct. There are no leakage currents.

3. Normal case, for example at VM=24V, is there any internal path from VM to control pin?

The path is from VM through the DVDD regulator through the pullup resistors to the pins.

4. Do other pins(RREF etc) have any leakage current to VM pin or other pins(other than GND)?

The path is from VM through the AVDD regulator through the current source to the pins.

5. Do you have any concern for the the control & power up sequence? Is this device the sequence free?

No concerns. The device is sequence free. There is one note in the datasheet:

On power-up or when exiting sleep mode, keep the STEP pin logic low, otherwise the indexer will advance one step.