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DRV8830: duty cycle question

Jenna Denhaan
Prodigy 50 points
Part Number: DRV8830
Other Parts Discussed in Thread: DRV8838, DRV8837

Can you help with the DRV8830 questions below:

  1. The duty cycle and voltage correlations do not appear to be linear (in 8.2.3 Application Curves section). Can you help to provide duty cycles for 6V, 6.5V, and 6.8V?
  2. We need pulse width to be 100ms and pulse to pulse delay to be 3000ms. Is this something that the DRV8830 be set to?

  • 0
    TI__Guru** 114905 points

    Hi Jenna,

    The DRV8830 is not intended for your stated application.

    The DRV8830 is designed to provide a constant voltage across the motor. The internal PWM generator, Integrator, and DAC work together to create a voltage from 2.57V to 5.06V.

    Average voltages above 5.06 cannot be achieved.

    Also the DRV8830 is designed to operated at low duty cycles during motor startup and increase the duty cycle to achieve the desired voltage. This can take up to 12ms.

    Please consider the DRV8837 or DRV8838 as alternatives. These devices are designed to allow higher VM voltage, and user controlled outputs.

  • 0 in reply to Rick Duncan
    TI__Prodigy 50 points

    A couple clarifications - sounds like duty cycle is not dependent on VCC then, correct? I saw in section 8.2.3 of the DS various duty cycles at VCC = 4.5 V, VCC = 5 V and VCC = 5.5 V, so I wanted to understand what duty cycle would be for the upper limits of VCC (6V/6.5V/6.8V) under the same conditions. Can you share this, or how to calculate this with these VCC values? Understand that we're limited at the output to up to 5.06V. 

    Also, for the second question - we need pulse width to be 100ms and pulse to pulse delay to be 3000ms - can the device be set to this? 

  • 0 in reply to Jenna Denhaan
    TI__Guru** 114905 points

    Hi Jenna,

    A couple clarifications - sounds like duty cycle is not dependent on VCC then, correct? I saw in section 8.2.3 of the DS various duty cycles at VCC = 4.5 V, VCC = 5 V and VCC = 5.5 V, so I wanted to understand what duty cycle would be for the upper limits of VCC (6V/6.5V/6.8V) under the same conditions. Can you share this, or how to calculate this with these VCC values? Understand that we're limited at the output to up to 5.06V. 

    The duty cycle is dependent on both VCC and the VSET value.

    A rough calculation for the duty cycle will be the lower of 100 * (VSET_OUTPUT_VOLTAGE/ VCC) or 100%. This assumes the current is below the current limit described in section 7.3.3 of the datasheet.

    Also, for the second question - we need pulse width to be 100ms and pulse to pulse delay to be 3000ms - can the device be set to this? 

    No, the device cannot be set to this. Sorry if I was not clear.

  • 0 in reply to Rick Duncan
    TI__Prodigy 50 points

    Thanks, Rick. In this case, what device would be a better alternative  to the DRV8830 that can meet the pulse width and pulse to pulse delay requirements?

  • 0 in reply to Jenna Denhaan
    TI__Guru** 114905 points

    Hi Jenna,

    You may have missed this in the original reply:

    Please consider the DRV8837 or DRV8838 as alternatives. These devices are designed to allow higher VM voltage, and user controlled outputs.