• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 30 subscribers
  • Views 189 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DRV2700 output clamped at a certain voltage

DRV2700: Output Slew Rate data, Fig15

Takumi Suzuki1
Mastermind 8610 points
Part Number: DRV2700

Hi,

Let me ask you a few questions about Fig15, datasheet 8 page as below.

Q1) Though the input signal level is around 0.65V, the output becomes 105V @G=40.8dB.

       I suppose that the output should be around 70V (=0.65V * 40.7dB)...

      Will you tell me the reason why output becomes 105V?

Q2) Difference between "rising edge time" and "falling edge time"

       The "rising edge time" seems to be longer than "falling edge time", especially in case of 1uF load.

       I suppose both time should be almost same...

      Why is the falling time shorter than rising? 

Thank you very much for your support in advance.

Best Regards,

  • 0
    TI__Guru* 84915 points

    Hi, Takumi,

    1) Your calculation is correct, we should expect a lower voltage if the differential input is 0.65V. This makes me think that probably the input voltage in this case is just the voltage in one input. I mean, the differential input should be twice 0.65V (around 1.3V). This makes more sense since it seems that the output voltage is clipping in figure 15 (the output reaches the PVDD level).

    2) Let me find more information about this. I will come back with you after consulting our design team.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Mastermind 8610 points

    Hi Luis-san,

    Thank you for your reply.

    About Q1), I understood.

    About Q2), I will wait for your reply.

    Again, thanks for your support.

    Best Regards,

  • 0 in reply to Takumi Suzuki1
    TI__Guru* 84915 points

    Hi, Takumi,

    Sorry for my late reply.

    I got more information from the design team. Basically, the output of the DRV2700 amplifier is in a particular push-pull configuration. This configuration plays a especial role in the slew rate since in the rising edge, the output is being driven by an internal diode. However, during a falling edge transition, the output is routed to a internal switch with low impedance. This architecture results in a slow rising edge versus a fast falling edge. This confirms the behavior of the plots in the datasheet.

    Please let me know if you have additional questions or comments on this.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Mastermind 8610 points

    Hi Luis-san,

    Thank you so much for your great support !

    I understood well.

    Best Regards,