Once in SLEEP state the data sheet says that the FETs are held off by weak pull downs (150K nominal according to the data sheet).
The data sheet also says that it takes up to 100us from nSLEEP going low until the chip is actually in SLEEP mode.
What happens if nSLEEP is asserted low while FETs are turned on?
It would be logical that nSLEEP be gated with the IN1 and IN2 signals such that at the beginning of the 100uS period the FETs are turned of normally (using IDRIVE level gate current), and then the chip switches to the 150K pull downs.
But that isn't documented anywhere.
If the chip simply applies the 150K pull-downs while the FETs are on, they will turn off very slowly. For example, if Vth is 3V, the pull-down will sink only 20uA, and a FET with a gate-drain charge of 5nC will take 250uS to turn off. If there is any significant load current flowing the FETs will experience very high stress during that time.
My question: is it safe to assert nSLEEP while the FETs are on and carrying load current?