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DRV8350: Own hardware with DRV8350

Daniel Mueller
Intellectual 890 points
Part Number: DRV8350

Hello Guys,

I’ve built my own hardware for a three-phase-inverter but I’m not sure if I did everything right since the drv gets damaged at higher currents sometimes. (around 60A-70A)

The problem doesn’t occur anymore since I lowered the IDrive (this was two days ago), but I wanted to make sure that my schematics are correct. Could anyone please look into the circuit?

One mistake that I made is that I connected VDRAIN and VM directly at the drv together instead of doing it like the in the layout example in the datasheet.


I also have some spikes on the gates of the mosfets at higher currents. Where could they come from?
I attached some pictures after the schematics.

Hardware:
Gate driver: DRV8350 -> IDrive: 100/200 mA
Mosfet: MTI85W100GC -> Qgd: 18nC

 

Thank you in advance.

 

 

Schematic:

Gate driver circuit:

 

Mosfet circuit (note: I changed the gate resistors to 0 ohm because of using IDrive):

 

Current sense circuit - phase A and B, phase C look the same (note: D9 and D8 are not populated, R73 and R71 are set to 0 ohm):

 

Board layout (80x70 mm):

 

 

Here are the pictures of the PWM signals of phase c. The signals of the other phases look the same.

PWM at no load (no spikes): Yellow GHC, blue GLC and pink phase C

 

PWM at 4A load (spikes are visible – it is not pictured but the spikes then also occur on the pwm signal before it gets into the drv):

 

 

PWM at 10A load (spikes getting bigger):

 

This is the current waveform of phase C (10A):

  • 0
    TI__Mastermind 22186 points

    Hi Daniel,

    Thanks for posting your question to the MD forum!

    We reviewed the schematic and it looks good, but I wanted to clarify a few things.

    1. I noticed the schematic symbol pins for the DRV8350 were labeled for the DRV8350S. I wanted to confirm that you are using the DRV8350H in your design.
    2.  What is the voltage ratings for the capacitors you are using on the VM, CPL, DVDD, VDrain-VCP pins?
    3. What commutation method are you using? Trapezoidal or FOC?
    4. Since the spikes occur on both the DRV PWM input and on the PWM output to the gates, there are a few possibilities:
    1.  The spikes are occurring on the ground or on the power rail. Would you be able to probe the power supply at the same time as the gate voltage to see if the spikes correlate? Also can you repeat that process and test the ground near the DRV as well?
    2. If you are using FOC commutation the spikes could be a result of the switching of the other FETs. Can you plot all three phases of GHx together with one of the high side PWM inputs?

    Regards,

    Anthony

  • 0 in reply to Anthony Lodi
    Intellectual 890 points

    Hello Anthony, thank you for answering and reviewing my schematic.


    Schematic:

    1. Yes, I’m using the DRV8350H (I didn’t find another model for eagle).

    2. Capacitors:

                        VM: 100V 0.1uF X7R 0805 10%

                        CPL/CHP: 100V .047uF 0603 X7R 5%

    DVDD: 100V 1uF 0805 X7S 10% (x > 6.3V)

    VDrain- VCP: 100V 1uF 0805 X7S 10% (x > 16V)

    (VGLS: 100V 1uF 0805 X7S 10%) (x > 16V)

    (VDD = VM & VDrain: 4x 100V 220uF 20%)

    3. I’m using FOC (Instaspin-FOC)



    How bad is it that I connected VM and VDRAIN together directly instead of splitting them? (Like it is done in the DRV8350 datasheet)

    Left: my schematic – Right: example datasheet

    Spike:

    1: VDD/GND and gate voltages.

    VDD at input of the board (pink) -> spikes are slightly visible
    GHA (yellow - voltage*10, wrong setting)
    GLA (blue)

    Same as above, just a few seconds later:

    GND near DRV – GND power supply (pink), GHA (yellow), GLA (blue):

    2: High sides gate voltages and PWM high a.

    GHA (blue)
    GHB (pink)
    GHC (yellow - voltage*10, wrong setting)
    PWM_HA (darkblue)

    Same as above:

    GHA (blue), GHB (pink), GHC (yellow):

    I think it is the second thing you mentioned, looks like the spike occurs when I’m switching the other FETs.

    Is there something that I didn't consider in my schematic or layout rather?

    Is there something that I can do against it?


    best regards

  • 0 in reply to Daniel Mueller
    TI__Mastermind 22186 points

    Hi Daniel,

     

    Thank you for providing the additional information!

    Regarding your capacitor voltage rating: if Vdrain is 50V or less than those capacitors will work great. 

    To answer your question about attaching VM to Vdrain directly: That may not be an issue as long as the voltage at the Vdrain/VM pins are close to the voltage at the L+ pin on the MOSFETs. The reason the voltage at these points need to be close in value is because the Vdrain pin is used to monitor the drain voltage of the high side MOSFETs and is also used to determine how much voltage the charge pump will supply to the gates. Therefore you want the Vdrain pin to accurately monitor the L+ of the MOSFETs. You can confirm this by testing the voltage between the L+ and VM/Vdrain pins while the motor is in normal operation.

    From the images you provided it looks like the spikes are due to the switching of the other phases. This could be a result of your Idrive setting still being too high for your design. I would recommend tying the Idrive pin to ground to achieve a 50mA/100mA Idrive current and see if that helps solve the ringing issue.

    Let me know if you have any further questions,

    Anthony Lodi

  • 0 in reply to Anthony Lodi
    Intellectual 890 points

    Thank you Anthony for the explanation of VM and VDRAIN.

     

    I reduced the IDrive to it's minimum but that didn’t change anything. Then I started to measure the gates with a ground spring (instead of a wire) at the probe. After that the spikes/ringing disappeared.

    I think that was it. Unfortunately, I blew up my gate drive with the probe at the second gate. I will get some DRVs this week and try it again with a differential probe or something. I will write you again if I’m sure that was it or not.

  • 0 in reply to Daniel Mueller
    TI__Mastermind 22186 points

    Hi Daniel,

     

    I'm glad to hear that you may have found the solution to the issue! I'm sorry to hear that the gate driver blew up. Please don't hesitate to reach out to us with any other questions you have.

     

    Thanks,

     

    Anthony

  • 0 in reply to Anthony Lodi
    Intellectual 890 points

    Hello Anthony,

    I replaced the DRV and took a few new measurements. It is a bit strange because it depends on what I measure whether or not the ringing occurs.

    I would like to show you what I did and maybe you can help clarify what it could be.

     

    I have to say I have not done everything correctly on my layout, maybe that is my main problem.
    For example I didn’t separate the grounds under the DRV, its just one. I will design a new one, unfortunately I saw the “Best Practices for Board Layout of Motor Drivers” pdf after I designed my board.

     

    This is MOSFET chip:

    at first, I measured between G6(GLC) and S6(SLC) (with the ground spring):

    This is between G5(GHC) and S5(SLC):

    I think the pictures above look not bad, I can’t see spikes but when I measure between G5(GHC) and S6(SLC) they appear:

    Also, on the phase (between S5(L3) and S6(SLC)):

    Do you think it is just a measurement artifact or could my layout cause the ringing? Maybe both?

  • 0 in reply to Daniel Mueller
    TI__Mastermind 22186 points

    Hi Daniel,

    Thank you for your response and the additional scope plots!

    After reviewing the plots there is nothing concerning that I see. The first two plots showing the high side and low side VGS looks good, which is important since the device monitors VGS. The third plot is not concerning since the device doesn't monitor the high side gate in reference to the low side source. If you wanted a more accurate picture of what the device would be monitoring you can measure VGH in reference to the device ground (instead of SLx). The device ground is often slightly different than SLx due to some inductance on the low side FETs. The final plot showing the Vds of the low side FET is not concerning either, since I believe the device only monitors VHS to the device ground, not to SLx. Even if it does, you are well within the absolute ratings of the device and isn't something to be concerned about.

     It is up to you if you want to redesign your layout to accommodate some of the techniques from the "Best Practices for Board Layout of Motor Drivers” pdf.  You may not need to redesign the layout, but if you do you can privately share your layout for us to review before manufacturing.

    Regards,

    Anthony Lodi

  • 0 in reply to Anthony Lodi
    Intellectual 890 points

    Hello Anthony, sorry for the late reply, I had an exam.

    Ok, that sounds good. If I measure between GND instead of SLx it is better with the ringing (Just for testing I added a snubber and the ringing almost disappeared).

    It works at 100A without any problems. Thank you, a lot, for clarifying if my board works correctly.

    I am redesigning it because it’s my first version and there are also a few other things I would like to change (e.g. more space for the heatsink). Thank you for the offer, I will come back to it in a few days.

  • 0 in reply to Daniel Mueller
    TI__Mastermind 22186 points

    Hi Daniel,

    I'm glad we were able to help! Please let us know if you have any other issues.

    Regards,

    Anthony Lodi