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DRV8353R: Unused SPx pins with VDS over current sensing disabled on DRV8353RH

Ross Hoag
Prodigy 80 points
Part Number: DRV8353R

My question is related to the unused SNx pins when using only SNA and SPA and a single sense resistor on my three phase bridge. I left them disconnected in my prototype board then relaized that at least SPB and SPC should be tied to the commong source point on the bottom FETS (the top of the sense resistor node) if the VDS over current sense is enabled. My question is if VDS over current sense is disable (pulled to VDD on the 8353RH) do they still need to be connected? I had things working for a brief period then killed my chip with too much gate drive (I suspect). I am getting ready to bring the next board up but before I do I want to understand if I need the source sense SPB and SBC tied to the proper source point or if I can leave them as no connects (IF the VDS over current sense is disabled)? I can see that if the VDS overcurrent sense was enabled and those pins were left floating bad things would happen and a fault would be likely. 

Also what about the actual amplifier outputs for the sense resistors, do they just pass on the amplified analog sensed voltage or is there any other internal fault detection that those outputs could trigger? . This goes to my quesiton above and is related to leaving the other side of the amp input left unconnected (SNB and SNC). Will that cause any issues? I can't see where it would but I want to make sure. 

Thanks,

Ross 

  • 0
    TI__Guru 65390 points

    Ross,

    SPx is the return path for the gate drive current so you should always connect the respective SPx to it's FET source.

    For unused CSA, you should connect the CSA inputs to GND (both SPx and SNx) and leave the SOx floating.

    This ensures that there is no differential voltage from SP to SN and the output is not trying to drive current into the GND since SOx normally sits at VREF/2 when SP-SN = 0.

    Regards,

    -Adam

  • 0 in reply to Adam Sidelsky
    Prodigy 80 points

    Just to be clear from your response above. 

    Are you saying I should connect the unused SBP and SBC to the sourses of thier respective FETs (the top of the bridge sense resistor)? I get that, given that is the way SPA is wired. note SNA wired to the bottom of the sense resistor. 

    Your second statement seem to conflict with the first part of your response - it does not make sense to me.  I would think that both SNB and SNC, if unsed, should be shorted to SPB and SPC, which from your first statement are tied to the source of the FET (top of the sense resistor) not GND...Am I missing something?

    My plan to address my proto mistake would be to short SPB and SNB together then to the source of the FET (not ground) then do the same for SPC and SNC. This ties the two inputs of the amp together as you suggest causing the vref/2 output with zero input while keeping the SPx pins, which are the gate return paths, tied to the source of the FETs. 

    Is this correct? 

    It will be easier to tie my noconnects to togther then to the proper return points, rather than make 4 connections total since the pins are next to each other. 

    Let me know your thoughts. 

    Ross

  • 0 in reply to Ross Hoag
    TI__Guru 65390 points

    Ross, 

    Your plan above makes sense.

    In the end, we simply to not want the CSA inputs floating and to make sure they aren't we short SP to SN. This can be on the top of the sense resistor for closest tie to the FET true source or at the bottom of the sense resistor since the difference between the top and bottom of the sense resistor is very close in voltage and proximity to the FET.

    Regards,

    -Adam

  • 0 in reply to Adam Sidelsky
    Prodigy 80 points

    Thanks for the reply, I am good to go and have things working.

    I am currently ramping up the gate drive current to ensure optimal drive and signal integrity. 

    Thanks again for your help. 

    Ross

  • 0 in reply to Ross Hoag
    TI__Guru 65390 points

    Ross,

    I forget if we checked your IDRIVE settings against your FET parameters.

    Could you let us know your IDRIVE settings used and FET QGD? Also are you using gate resistors?

    Regards,

    -Adam