DRV8833C: driving resonant L-C circuit

Hi Martina,

I apologize for the late response.

The first thing to consider is the resonant frequency. The resonant frequency should be less than 200kHz which is the maximum recommended PWM  frequency for this device. Another thing to consider is the blanking time (t_blank). The t_blank for this device is around 3.75µs and is the time right after the outputs are enabled where the xISEN pin voltage is ignored before enabling the current sense circuitry. The resonance period should be greater than 3.75µs (~266kHz).

Hi Martina,

3) Regarding your answer:

a) For a resonant frequency below 200kHz, the resonance period is greater than the blanking time (3.75 µs) in any case (T=1/f). Am I missing something?

A: What I meant to say is that the resonance frequency should be less than 266kHz to ensure its period is greater than 3.75µs. However, the maximum PWM frequency rating for this device is 200kHz. So if the resonant frequency is below 200kHz as recommended, the resonant period will always be greater than 3.75µs. I apologize if my previous response caused confusion. 

b) Does this blanking time apply once (after nSleep is set to high for enabling the device), or does it apply every period (starting whenever current >0 is driven from one of the outputs)?

A: The blanking time occurs every-time the outputs switch states (going from High-to-Low and vise-versa), The blanking time is needed to ensure that the current is stable enough for monitoring. 

c) Does the blanking time need to be considered, when current control is not needed?

A: Even if current regulation is not being used, the blanking time should still be considered. 

4) Assuming a resonance frequency between 120kHz-140kHz:

a) What happens when the resonant circuit is driven below / above resonance? This includes scenarios in which the driver sees a capacitive load. Does the driver support this?

A: the driver should be able to support this scenerio as long as the frequency does not go above 200kHz.

b) Can the driver be driven with a PWM at XIN1 and the inverted PWM at XIN2? What needs to be considered regarding this? How do the different decay modes of the driver come into play regarding this, and what is their effect on the output current? What is the maximum delay that the inverted PWM should have with respect to the PWM?

A: XIN1 and XIN2 inputs should follow the control tables shown in the datasheet. If you have inverted PWMs in both XIN1 and xIN2 (assuming there are no overlapping section between the two PWM signals), then according to the control table, the outputs will just be changing direction (forward and reverse) without entering decay mode. Decay mode happens either when both xIN1 and XIN2 signals are LOW or HIGH.  

c) What needs to be considerered regarding different duty cycles ( between 10% and 50%)? Does the driver go into different modes for different duty cycles?

A: The driver sets the outputs to different decay modes depending on the overlapping sections of both PWM signals. If both signals overlap when both signals are low, then it goes to brake/slow decay mode as described in Table 1. In the case that both PWM signals overlapp when both are HIGH, then the outputs go into coast/fast decay mode. In the case that you have inverted PWMs with both HIGH and LOW overlapping regions. Then the outputs will be alternating between coast/fast decay mode and brake/slow decay mode.