1.Eight drive chips were used in the project in series,Signal format I think it's HDR1+HDR2+A8+A7+A6+... +A1+D7+…+D1，Is the signal of scs always low during data transmission？
2.If I wanted to write a value into a register, would the register address be the address shown in Table 14 Memory Map? multiple DRV control chips are connected in series, the addresses are the same?
3.Is the chip's spi timing an idle low, a falling edge capture, or an idle level high falling edge capture？
