• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 29 subscribers
  • Views 465 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8350: Layout for VM and VDRAIN PIN

Brian Wang0928
Genius 13160 points
Part Number: DRV8350

In the D/S's page 78, it addresses layout recommendation as below.  

The VDRAIN pin can be shorted directly to the VM pin for single supply application configurations. However, if a significant distance is between the device and the external MOSFETs, use a dedicated trace to connect to the common point of the drains of the high-side external MOSFETs. Do not connect the SLx pins directly to GND. Instead, use dedicated traces to connect these pins to the sources of the low-side external MOSFETs. These recommendations allow for more accurate VDS sensing of the external MOSFETs for overcurrent detection.

However, on the page 7, VDRAIN PIn is far away from VM pin. I'm confused about this. please help to clarify which layout is better for noise immunity? Very thanks. 

  • 0
    TI__Intellectual 840 points

    Hi Brian,

    The VDRAIN connection on the part is a sense line only. Our goal is to most accurately sense the voltage at the drain of the high side FETs, as this is the drain the VDS monitor relies on. If you connect VDRAIN right at the part to VM and the voltage of the high side drain is different due to trace inductance, the VDS monitor will not have an accurate reading. Routing the VDRAIN and SLx traces all the way out to the power stage as mentioned in the datasheet allows for kelvin sensing on these nodes. Page 79 actually an illustrates the suggestion on page 78 when the power stage is a significant distance from the DRV8350.

    Best regards,

    Omar