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DRV8873-Q1: register configuration is reset to default when VM's power supply drops to 4V

Part Number: DRV8873-Q1

Dear team,

My customer is testing our device recently. When they did some test items, the MRIGN power which is the VM's power supply will drop down to 4V, and 4V exceeds our recommendation range(4.5V-38V). When the power supply drops down to 4V, our 8873 will be restored to default settings. Their default setting is PWM mode, but the customer needs PH/EN mode actually. Because the system is still working, control signal output continuously, they can't  reinitialize the 8873 to enter the correct PH/EN mode after VM's power becomes normal.

My question is,

Why our device will be restored to default settings when the power drops to 4V?

Is there any workaround about this issue? Change the default setting to PH/EN mode? But how? Or power the DVDD pin with external VCC power?

Thanks & Best Regards,

Sherry

  • Hi Sherry,

    The logic core will be reset when the VM supply drops below the UVLO reset threshold of 4.1V  (Vrst parameter in the datasheet).

    DVDD is internally regulated from VM and cannot be supplied externally (the DVDD pin is there only for providing local de-cap).

    For the SPI device, if the VM supply can drop below spec, then this must be accommodated for in software.  We have the nFAULT pin which will be asserted during the UVLO event.  This could be monitored by the microcontroller, and trigger an interrupt, letting the MCU know it must stop asserting the EN/ PH signals, and reprogram the registers when the UVLO condition is cleared.  The device also fault status registers that will store the UVLO flag, and should be polled periodically if the nFAULT interrupt is missed.

    The other option would be using the hardware variant of the device, which does allow hard-wiring the device mode.  I assume your customer selected the SPI device for the flexibility, and this is not really a good option, but wanted to at least mention this.

    Regards,
    Mike