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DRV8703-Q1: question to timing characteristic.

Soichi Nishimura
Expert 5245 points
Part Number: DRV8703-Q1

Hi team,

I have some questions to DRV8703-Q1.

(1) The following are four temporal characteristics listed in data sheet 6.7.

Is it possible to detect that these times have past (sequence completed) by output or communication from the gate driver IC?

(2) This is t(on),t(SPI_READY) described in datasheet 6.7.

Does t(SPI_READY) include the time for t(on)? Or does t(SPI_READY) include the time of t(on) after t(on)? 

Below is the image that I questioned.

Regards,

Nishimura

  • 0
    TI__Guru 56650 points

    Hello, Nishimura-san,

    1. t(sleep), t(wu) and ton's test conditions indicate that timing detection from by output change. But, the output cannot be used to check the t(spi_ready). Would you check the nFault pin waveform when VM>VUVLO1?

    2. ton happens at VM>VUVLO2;  t(spi_ready) happens at VM>VUVLO1. I agree with the top timing chart.