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DRV8353RS-EVM: DRV8353 used inverter design.

Part Number: DRV8353RS-EVM
Other Parts Discussed in Thread: DRV8353

Hi,

I am Thanseela, I am designing a motor controller. In this design we are using DRV8353 as mosfet driver. So please clear my below queries. We are using  4*2 mosfets/leg.

1.What about gate resistance requirement while using DRV8353?

2.Phase return lines need to take from each mosfets?

  • Hello Tanseela,

    Can you confirm that you're using 4 MOSFETs in parallel for a total of 8 FETs used between the GLx and GHx pins for a specific phase or leg (such as 4 parallel gate connections to FETs for GHA and 4 more for GLA)?

    1.What about gate resistance requirement while using DRV8353?

    Technically there is no requirement. The smart gate drive architecture replaces the need for the gate drive resistor as gate drive resistors simply result in a changed rise and fall time to the FET. The adjustable gate drive current within the device will do the same thing. However, feel free to put a 0 ohm resistor in series with the gate just in case it needs to be adjusted in-between the various settings that our device can offer.

    It is really really really really really really important that you choose the correct IDRIVE setting. Please consult the FAQ linked below for the equation to calculate the correct IDRIVE. Just use the QGD from the FET's datasheet and use 100ns to start for the rise and fall time. You might want to go faster but please build your board and test at that use case before decreasing the time.

     

    2.Phase return lines need to take from each mosfets?

    SHx is the return line for source the high side FET and SPx is the return line for source of the low side FET.

    GHx and SHx, therefore, are the paired signals which are used for functional, protection, and sensing signals should treated “like” differential pairs where lengths, widths, and loop shape should be similar or the same size for the pairs (not necessarily every A, B, C half bridge needs the same specs).

    In the case of parallel MOSFETs, the SHx, or phase node, needs to be located "equidistantly between the sources of all high side MOSFETs for specific phase". Think of a star connection where the common point splits into 4 traces of equal length at connect to the gates of the MOSFETs. Otherwise, the equivalent impedance between the sensing pin (SHx) will be higher for some FETs compared to others, which means the protection will be less likely to sense voltage transients through the larger impedance.

    Best,

    -Cole

  • Can you confirm that you're using 4 MOSFETs in parallel for a total of 8 FETs used between the GLx and GHx pins for a specific phase or leg (such as 4 parallel gate connections to FETs for GHA and 4 more for GLA)?

    Yes

    I am sharing two way routing. Please suggest which is the best way of routing phase return lines.

  • Hello Thanseela,

    Looks like your layout pictures were broken. Can you use the attach picture button in the reply box specifically instead of of copying and pasting? Please include the schematic as well.

    As for your plan, I find it very interesting that you are using 8 FETs for each leg. I have never seen any other user use 4 specifically. I have seen 3 and that was for redundancy as they admitted that 2 was good enough for their power level. This means you've decided to use more FET then what the market typically uses or you're trying to drive way more current than the typical user. As such, if you are looking to driving 1000s of Watts I suggest you be very careful and add way as much voltage protection circuits to the power stage (snubbers, clamps or diodes, GS caps, mF's of decoupling capacitance) as you can. 

    Best,

    -Cole