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DRV8353: DRV8353H

Part Number: DRV8353

Hi,

I am developing 3 phase SRM drive with DRV8353 gate driver in independent mode pwm. With this mode, the top mosfet gate voltage with respect to ground  is not going zero instead it is coming as gate voltage pwm + bus voltage(48v). Due to this, the top mosfet always is in always high condition irrespective applied pwm.Refer below waveform,

We removed VGS resistor diode (D10, R104), still same result. Please help me to sort out this problem.

Regards,

Kumar

  • Hi Kumar,

    Thanks for reaching out on the TI E2E forum! The second image (which I believe is a schematic) is broken, could you retry posting the image?

    Best regards,
    Omar

  • Hello Omar,

    Thanks for your reply. Here is the Schematic Picture.

    Regards,

    Kumar

     

  • Hello Omar,

                  Herewith I have attached DRV8353H RTA schematic.

    Best Regards,

    Kumar 

  • Hi Kumar,

    I am assuming that the phase C load is connected between C1 and C2. With that said, I would first guess that this is caused by the DRV8353 architecture. The high side driver allows a small leakage current out of the SHx pins when the charge pump is active (when ENABLE is high.) This leakage current is on the order of ~200-600uA and will be dissipated as soon as the low side FET is turned on. GHx - SHx is the VGS voltage of the high side FET and when the high side FET is OFF then GHx will be internally connected to SHx. Therefore, no VGS voltage can develop and the high side FET is guaranteed to be OFF.

    To confirm that this is the case, can you take a differential measurement of GHx-SHx with the high side input both high and low? Alternatively, if you have a differential probe available you could take a scope capture while PWMing INHx and measuring GHx-SHx for that channel. What you should see is GHx-SHx going to zero when INHx is low.

    Best regards,
    Omar