• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 29 subscribers
  • Views 460 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8889-Q1: nSCS Minimum High Time

Shinichi Yokota
Genius 9715 points
Part Number: DRV8889-Q1


Hello,

I'd like to know about the Min high time of DRV8889-Q1's SPI nSCS signal, but its data sheet specifies 2 µs as the t(HI_nSCS)'s Max value. Is it mistaken for the Min one? Again, what I'd like to know is at least how long the nSCS must stay High before changing it to Low.

Best regards,
Shinichi Yokota

  • 0
    TI__Genius 13505 points

    Hi Yokota-san,

    The spec is correct (admittedly confusing).  The meaning is nSCS must be deasserted (high) for a minimum of 2us before asserting (low).  So for a series of SPI transactions, there must be a 2us delay inserted between each data transfer.  This would be potentially important if there was a tight loop polling a register value, for example.

    Regards,
    Mike