BOOSTXL-DRV8323RS: DRV8323RS MOS_GS_Drive signal check

Hello, and thank you for your question.

1. The gate waveform is not an exact square wave since you are driving current into the MOSFET gate (which is like a capacitor). This current causes the voltage at the gate to increase over time. It cannot be a perfect square wave, there will be some rise time.

2. Can you confirm how you are measuring the low-side gate waveform? The low-side gate pulls down to the PGND pin. If there is some difference between PGND of DRV8323R and the MOSFET GND then you could measure some offset on the oscilloscope. It sounds like there is no issue during operation (the low-side MOSFET stays OFF) so I think this may be a measurement error.

3. The high-side gate drive voltage is generated by a charge pump, and this charge pump has a certain transient current capability. When you have a high IDRIVE or drive multiple high-side MOSFETs simultaneously, the charge pump voltage will drop some. The charge pump will then work to increase the VCP voltage over time. This can result in some ripple observed on VCP which will also be seen on the high-side gates. There should be no issue during operation even if this ripple is seen.

Thanks,

Matt

Hello,

1. The recommendation to remove R42 is to see if disconnecting the SDO pin from the rest of the circuit has any effect on the rise time that you can observe. This would isolate the SDO pin.

2. The best GND location would be AGND pin 35. However if there is a strong ground connection it should not matter. Is there any issue in SPI communication happening?

3. tD_SDO is fixed internally to the DRV8323R

Thanks,

Matt

Hello,

Since the SPI communication is functioning properly, I do not think there is an issue. If SPI communication issues were occuring, we could slow down the SPI clock, but I don't think it is necessary.

Thanks,

Matt

Hello!

From Figure 8 in the CSD18540Q5B datasheet (assuming 10V VGS) we can derive that the normalized RDS(ON) at temperature is approximately equal to (1.07e-5 * T^2 + 2.93e-3 * T + 0.92), meaning at 120C, our factor is 1.43x. On a typical unit (assuming 10V VGS) with 25C RDS(ON) = 1.8mΩ, the 120C RDS(ON) will be 2.57mΩ. However, the worst-case RDS(ON) at 25C is 2.2mΩ. Therefore the worst-case RDS(ON) at 120C is 3.14mΩ.

You want to make sure that the overcurrent does not trip during normal operation, so you need to ensure that the maximum (peak) operational current is under the VDS_OCP setting.The overcurrent deglitch time is only a few microseconds, so any peak current may trip the monitor.

For example, if you have a continuous current of 29A but a peak current of 40A, you should set the VDS such that VDS > 3.14mΩ x 40A = 125mV. We recommend at least +30% margin to be sure OCP does not accidentally trip, and so a setting of 200 or 260mV seems reasonable. If you run into overcurrent faults that are unexpected, you can always raise the limit to the next highest setting.

Thanks,

Matt

These are good questions!

1. Normally we can approximate the "peak of the waveform" or "highest current" or "top of the sine wave" to be IRMS * sqrt(2). In your oscilloscope, you may be able to measure "MAX" or "PEAK" using a function.

2. I did an Excel Curve Fit on the black line of Figure 8. According to the quadratic curve fit function, it is approximately (1.07e-5 * T^2 + 2.93e-3 * T + 0.92) when using the following points: (-50C, 0.8), (25C, 1), (75C, 1.2), (150C, 1.6). This should be representative of the expected MOSFET change in RDS(ON) over temperature. This is a normalized value, not the actual RDS(ON)

3. The MOSFET will be current limited due to the construction of the package, the die itself, and thermal properties.

• In the 1st spec this is how much current the package is designed to handle (i.e. bondwires).
• The 2nd spec, this is how much current the die is designed to handle (i.e. die metallization).
• The 3rd spec is the expected current the MOSFET is capable of driving contiguously without exceeding the temperature rating. The 3rd specification is based on a board with RθJA= 40°C/W, and if you have a board with better thermal characteristics you can expect to drive higher current.

Thanks,

Matt

Hello,

At high speed you could be triggering a gate drive fault (latches OFF instead of retry) instead of an OCP fault. Can you check the register settings of the device after a fault is registered to confirm the fault type? You can read the first two registers to see what is the fault.

A couple things to try:

• Disable gate drive fault as an experiment by setting DIS_GDF = 1 (Address 0x02 bit 8)
• Decrease the overcurrent deglitch time by setting OCP_DEG to 2 us 00b (Address 0x05 bits 5-4)
• Decrease the VDS _LVL so that OCP trips at a lower voltage (Address 0x05 bits 3-0)

Thanks,

Matt

Hello,

The GDF threshold is between 1V and 2V, and so the gate has to be higher than this voltage to register as ON. When turning ON the MOSFET the DRV832x checks that the gate is higher than the threshold after TDRIVE time, when turning OFF the DRV832x checks that the gate is below the threshold after the TDRIVE time. As long as the gate voltage gets higher than 2V, it will not cause a GDF when turning ON the MOSFET.

It looks like the gate is forced high when it is trying to turn OFF due to the short on the motor. Since it does not shut OFF within 4us, a gate drive fault (GDF) is asserted and the device will shut down.

It may be good to observe the GHA, SHA, and GLA on the oscilloscope just before the fault occurs.

You may also try reducing the IDRIVE setting to see if the GDF fault goes away. We have seen some cases where the high gate drive current can cause oscillation which trips the gate drive fault.

Thanks,

Matt

Hi,

Faster switching is better because it reduces delay and switching losses, but there is always a limit on how fast you can drive the MOSFETs. If the slew rate is too high, you can cause ringing, EMI, or voltage over stress. If a board has significant parasitic inductance, that will limit how fast you can go.

We normally recommend between 100ns and 300ns rise time; Rise time = Qgd / IDRIVE. CSD18540Q5B has a Qgd of 6.7nC so we would recommend an IDRIVE between 22.3mA  and 67 mA. So the IDRIVEP setting should be 30mA or 60mA. The IDRIVEN can be set to 2x IDRIVEP, meaning 60mA or 120mA.

Thanks,

Matt

No problem! Please come back with any further questions you may have!

Hi,

The gate drive fault uses a threshold of about 2V.

• If the gate is measured below 2V after trying to turn ON, it is considered a fault.
• If the gate is measured above 2V after trying to turn OFF, it is considered a fault.

Thanks,

Matt

Hello again!

Under high current it does look like a small oscillation is introduced on the gate and phase waveform. This is normal because at higher currents the effect of the PCB trace inductance will be more. The oscillation is not very significant, and it does not exceed the voltage rating of the device.

I would recommend keeping with the 60mA setting for now in order to have lower switching loss. If you run into EMI problems later, you can decide if you need to further reduce the IDRIVE. I do recommend increasing TDRIVE to 1us for your 60mA setting and if you decrease IDRIVE to 30mA I would use 2us TDRIVE.

There are other ways to mitigate the oscillation on the board, for example adding snubbers to the output (like in this article: LINK).

Thanks,

Matt

Hello,

I am looking at the voltage at GHx and SHx in this case - I do not see these abs max pin voltage ratings being violated. This ringing may result in EMI, but from a driver standpoint it is not causing any dangerous voltages.

TDRIVE is normally set to be 2x the MOSFET charge time (Qg / IDRIVE). This parameter does not need to be very accurate, it just needs to be longer than the time it takes to charge the MOSFET gate. In your first waveform I see that the charge of the GHx takes longer than 500ns, so TDRIVE should be longer than 500ns. However there is no issue to use the maximum TDRIVE.

If you change to a different MOSFET, you may have to change IDRIVE. My suggestion is to choose an IDRIVE such that QGD / IDRIVEP is in the range of 100ns to 300ns. TDRIVE should be set to be at least 2x Qg / IDRIVE, or just use the maximum TDRIVE.

Thanks,

Matt

Yes, that is a very good question.

In your plot, the time from A to C is TDRIVE, and you can see that the MOSFET gate starts to charge more slowly after TDRIVE is done because the gate drive current switches from IDRIVE to IHOLD (the slope of the yellow trace changes at C). Ideally, you want to completely charge the gate before TDRIVE is done. So I can tell that TDRIVE is set too low.

The total charge time for the *gate* is from A to after C, because the gate is still increasing in voltage after C.

The charge time from A to B is the most important for the motor operation, because this is where the output (SHx) will switch including the miller region.

Thanks,

Matt

Hello,

QGD (miller plateau) is the most important factor in the voltage slew rate at the motor terminals, so QGD / IDRIVE  = 100 to 300ns is the guidance for the target rise and fall time on the output. This is the rise or fall time at SHx, not at GHx or GLx. In your diagram, the MOSFET VDS is switching between t2 and t3. t0 to t1 is a delay before the MOSFET begins to turn ON, and the current begins to flow in the MOSFET between t1 and t2. We do not count t1 to t2 to calculate the slew rate because the output voltage does not change during this time, even though the current is changing.

The MOSFET gate rise time is not as important for the system. This would be the time it takes for the GHx or GLx to rise from 0V to 11V (through QGTOTAL). We recommend making sure that TDRIVE is set to be greater than this time.

Thanks,

Matt