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OMAP4460 ISS: CSI2_COMPLEXIO_CFG (RESET_DONE) always remain low

sweta bhatt
Expert 2345 points
Other Parts Discussed in Thread: DM3730

Hi,

I have interfaced external sensor with J17 connector of OMAP4460 (Panda board-ES).

This sensor is outputting CSI clock and data on clock and data lanes available on J17 connector of Panda board-ES. From this connector, signals straight away go to OMAP4460 processor.

As per tech ref manual of OMAP4460, there is a caution that this bit (bit 29 of ) will be 1 only if external sensor is active and sending the MIPI HS BYTECLK.

I am using V4L2 driver release and in OMAP4ISS driver, there isn't any checking for this bit. Can someone please help me to get answers to following ?

1) If I am getting configured differential clock on CSI21_DX0 and CSI21_DY0, what can be wrong/reason why I am not getting internal module out of reset ?

2) Is MIPI HS BYTECLK same as the clock I am receiving on CSI21_DX0 and CSI21_DY0 ? How to ensure that MIPI HS BYTECLK is coming to ISS ?

3) REGISTER1[29:28] (0x52001174) mentions about "reset done read bits". I am getting both these bits as 0. Tech ref doesn't mention the description of value as 1 and 0 for these two bits. Is this expected value ? Can I assume that BYTECLK is provided to the ISS CSI2-A ?
Note - Reset for CSI2_96M_FCLK (CAM_PHY_CTRL_FCLK) is successful from driver code's status point of view.

Any help on above will be appreciated, I am stuck due to above.

Regards,
Sweta

  • 0
    Expert 1200 points

    We have the same problem. Can anybody help with this?

    Thanks in advance

  • 0
    TI__Mastermind 24525 points

    Most likely it is a timing issue - please check THS_SETTLE and THS_CLOCK

  • 0 in reply to Mayank Mangla
    Prodigy 120 points

    Hi all,

    I have a similar problem with DM3730. In my case, CSI2_COMPLEXIO_CFG1 was 0x4b0000a9, but it seems that I had a problem with lane configurations. It seems that lane position1 corresponds to CAM_D0/1, position 2 to csi_dx/y0 and position 3 to csi_dx/y1. Is this right? After changing data and clock lane configuration in that way, CSI2_COMPLEXIO_CFG1 is 0x6b0000ba.

    My problem now is with CSIPHY_REG1 that keeps at 0xC002E10E. This value means that CSI2_96M_FCLK domain reset is in progress and that RxByteClkHS clock domain reset is also in progress. CSI2_96M_FCLK is an internal clock that is enabled with CM_FCLKEN_CAM[1] (it is set to 1 in my system), so I don't konw why I can't take it out of reset. I'd like to know which is the condition to bring this clock domain out of reset.

    As per RxByteClkHS, I don't know which condition brings it out of reset but I guess that it may be related to detecting a valid HS clock in the lane, so I am  reviewing the configuration of my timings as I think that it may be related. Is my guess right?

    Thanks in advance.

  • 0 in reply to Andrew Mounts
    Prodigy 120 points

    Hi again,

    I didn't set up pulldowns as specified in the datasheet (6.5.2.1). After implementing that I get 0xF202E10E in CSIPHY_REG1what means that I have an error in clock missing detector. I have checked that there is clock signal so I suppose that this is related to the timings that are configured through this register.

    However, after reading the datasheet it seems that these are fixed values. In addition to that, I wonder whether the missed clock is the mipi one or the rxbyteclkhs which I can't measure.

    Please, can anyone provide some help about these timings and this error?

    Thanks in advance.

  • 0
    Prodigy 30 points

    I am also running into this problem.  Has anyone been able to resolve this issue?

    I have a wince driver that works just fine (though it too took a while to get up and running)... something is different and I have been spinning my wheels for a couple weeks.