Hello All,
I have a question about setting the drive strength (or buffer strength) for the I/O lines that we're using for our eMMC storage.
As background, we've hooked up a standard eMMC part (with 1.8V interface) to the OMAP4's SDMMC2 via the GPMC pins (gpmc_noe, gpmc_nwe, gpmc_ad[0-7]). This all works fine, and the system seems to run fine. However, looking at the data lines with an oscilloscope, we're seeing a bit more overshoot and ringing than we'd like.
In the next board revision, we're planning on adding some in-line low value resistors which should damp down that overshoot (and possibly reduce EMI too). However, in the mean time, the thought was to also adjust the drive strength of those lines both from the OMAP4 side as well as the eMMC side.
So looking at section 18.4.12.9.6 C2CI/O Cells With Load Setting Adjustable According to Interface Requirement Voltage Mode and Table 18-86. GPMC I/O Signal Group Parameter Controls to Different Interface I/O Pads Mapping in the TRM, it seems that the only adjustment for these I/O lines is to just set the the LB0 bit in the CONTROL_C2CIO_PADCONF_0 register. The default value is '0' at reset, which is correct for using these pads for SDMMC2 (for both 1.2V or 1.8V). It seems we are only to set LB0 to '1' if used in C2C mode or GPMC 1.8V modes.
So right now it looks like there is no useful adjustment to the drive strength for SDMMC2.
Is our reading of the TRM correct? Is there some other software means to adjust drive strength?
Thanks,
James