OMAP4 CSI2 PHY config issue

Attached is log of CSI2 registers and "show camera"

1805.csi2-cfg.txt

We have the same problem. Can anybody help with this?

Thanks in advance?

Please make sure that sensor is streaming and sending MIPI clock and data signals. Also you need to make sure that the sequence and timing of initialization is correct. The sequence is explained in TRM.

Finally you need to make sure that THS_CLOCK and THS_SETTLE parameters are set correctly as explained in the TRM.

Hi all,

I have a similar problem with DM3730. In my case, CSI2_COMPLEXIO_CFG1 was 0x4b0000a9, but it seems that I had a problem with lane configurations. It seems that lane position1 corresponds to CAM_D0/1, position 2 to csi_dx/y0 and position 3 to csi_dx/y1. Is this right? After changing data and clock lane configuration in that way, CSI2_COMPLEXIO_CFG1 is 0x6b0000ba.

My problem now is with CSIPHY_REG1 that keeps at 0xC002E10E. This value means that CSI2_96M_FCLK domain reset is in progress and that RxByteClkHS clock domain reset is also in progress. CSI2_96M_FCLK is an internal clock that is enabled with CM_FCLKEN_CAM[1] (it is set to 1 in my system), so I don't konw why I can't take it out of reset. I'd like to know which is the condition to bring this clock domain out of reset so that I can fix this.

As per RxByteClkHS, I don't know which condition brings it out of reset but I guess that it may be related to detecting a valid HS clock in the lane, so I am  reviewing the configuration of my timings as I think that it may be related. Is my guess right?

Thanks in advance.

Hi again,

I didn't set up pulldowns as specified in the datasheet (6.5.2.1). After implementing that I get 0xF202E10E in CSIPHY_REG1 what means that I have an error in clock missing detector. I have checked that there is clock signal so I suppose that this is related to the timings that are configured through this register.

However, after reading the datasheet it seems that these are fixed values. In addition to that, I wonder whether the missed clock is the mipi one or the rxbyteclkhs which I can't measure.

Please, can anyone provide some help about these timings and this error?

Thanks in advance.

Hello,

I have to revive this thread because I am experiencing the same issues with CSI :(

I can confirm the behavior that Andrew Mounts has observed: adding +1 to the lanes indexes indeed causes the CSI2_COMPLEXIO_CFG[29] RESET_DONE to get HI. Moreover, this is dependent on the state of the lanes, i.e. if there is no activity on the CSI wires, then the bit remains LOW. I have requested information directly from TI about this issue, but there is no reply so far. Otherwise,

However, I cannot get the REG1[28]: RESETDONERXBYTECLK to be set as in the last post of Andrew Mounts. Could it be that this depend so tightly on the timing values in REG1 and REG0 of the PHY layer.

Can someone give an example of how to configure these values, because from what I read in the TRM I cannot decide on the numbers?

And can someone confirm he/she is able to use the CSI at all, I couldn't find any success stories so far?

Thanks to whoever helps :)

A lot of people have been able to use CSI2 i/f. This forum is not for success stories and that's why you won't find them here.

>> if there is no activity on the CSI wires, then the bit remains LOW

This is expected and as per MIPI specification.

>> I cannot get the REG1[28]: RESETDONERXBYTECLK to be set

Please check CSI timing parameters and sequence of Rx/Tx init

Hi and thanks for the fast reply :)

So:

>>> if there is no activity on the CSI wires, then the bit remains LOW

OK, but I state that bit is set only when I supply +1 values for the lanes, which is not according to the datasheet.

>>> Please check CSI timing parameters and sequence of Rx/Tx init

Do you mean that REG1[28]: RESETDONERXBYTECLK won't be set until correct timing values are supplied:

REG0 [THS_TERM]

REG0 [THS_SETTLE]

REG1 [TCLK_TERM]

REG1 [TCLK_SETTLE]

Some hint for 108MHz clock?

10X :)