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CCP2 initialisation issue, no RESET_DONE set.

Other Parts Discussed in Thread: SYSCONFIG

Hi,

My task is to make OMAP4430 receive a data from FPGA over the CCP2 camera interface, throughput > 100Mb/sec. FPGA acts here as a camera sensor following "SMIA 1.0 Part 2: CCP2 Specification".

Problem is that I cannot make the CSI22 COMPLEX_IO get RESET_DONE bit set after initialisation. The initialisation sequence is shown below.

Could you, please let me know is there any source code which does a full CCP2 initialisation.

# PM_CAM_PWRSTCTRL

omapconf write 0x4A307000 0x00000003

# PM_CAM_PWRSTST

omapconf read 0x4A307004

 

# CM_CAM_CLKSTCTRL

omapconf write 0x4a009000 0x00000002

omapconf read 0x4a009000

 

# CM_CAM_ISS_CLKCTRL

omapconf write 0x4a009020 0x00000000

omapconf read 0x4a009020

omapconf write 0x4a009020 0x00000102

omapconf read 0x4a009020

 

# CONTROL_CAMERA_RX

omapconf write 0x4A100608 0x60240000

omapconf read 0x4A100608

# CONTROL_CORE_PAD0_CSI22_DX0_PAD1_CSI22_DY0

omapconf write 0x4A1000b4 0x01000100

# CONTROL_CORE_PAD0_CSI22_DX1_PAD1_CSI22_DY1

omapconf write 0x4A1000b8 0x01000100

 

# ISS_HL_SYSCONFIG

omapconf write 0x52000010 0x0000003D

omapconf read 0x52000010

omapconf read 0x52001450

omapconf read 0x52001574

 

# ISS_CLKCTRL

omapconf write 0x52000084 0xF0000010

# ISS_CLKSTAT

omapconf read 0x52000088

# ISS_PM_STATUS

omapconf read 0x5200008c

# ISS_HL_IRQENABLE_SET_5

omapconf write 0x52000078 0x000303c0

 

# CSI2_SYSCONFIG

omapconf write 0x52001410 0x00000003

omapconf write 0x52001410 0x00001000

omapconf read 0x52001414

 

# CCP2_SYSCONFIG

omapconf write 0x52001C04 0x00000003

omapconf read 0x52001C04

omapconf write 0x52001C04 0x00001000

 

# CSI2_COMPLEXIO_CFG

omapconf write 0x52001450 0x00000021

omapconf read 0x52001450

# CONTROL_CAMERA_RX

omapconf write 0x4A100608 0x60100000

omapconf write 0x4A100608 0x60340000

mapconf write 0x52001570 0x00000008

omapconf read 0x52001570

omapconf read 0x52001574

omapconf read 0x52001450

# CSI2_COMPLEXIO_CFG

omapconf write 0x52001450 0x40000021

# CSI2_TIMING page 1684

omapconf write 0x5200146C 0x7fffffff

# CSI2_COMPLEXIO_CFG

omapconf write 0x52001450 0x48000021

omapconf read 0x52001450

# CSI2_TIMING

omapconf write 0x5200146C 0x7fff7fff

 

omapconf read 0x52001570

omapconf read 0x52001574

omapconf read 0x52001450

 

Kind Regards

Dragan

  • I've seen similar issues with CSI-2 if the external sensor is not providing a clock.

  • Brad, thank you very much for the reply.

    Clock is present on dx0-dy0; FPGA generates 20MHz clock constantly, it creates periodicaly a small data frames on dx1-dy1 as well.

    Anyway there is no signal coming through COMPLEX_IO for me.

    CSI2 COMPLEX_IO initialisation is different than CCP2, acording to TMR.

    There is no mention of RESET_DONE in CCP2 chapter, it looks like that RESET_DONE is not needed in CCP2 init?

    My question is:

    1. is CSI2_COMPLEXIO_CFG (29:RESET_DONE) needed in CCP2 mode?

    2. is REGISTER1 (28: RESETDONERXBYTECLK Reset done)  needed in CCP2 mode?

  • Those are both CSI-2 registers.  The RESET_DONE bit pertaining to CCP is CCP2_SYSSTATUS[0], which is initiated through CCP2_SYSCONFIG[1] SOFT_RESET.

  • Brad,

    this answer clarifies many things. Thank you for that.

    still, I have problem: The data is not getting through COMPLEX_IO.

    My verification method is checking the events in the event register (CCP2_LC01_IRQSTATUS | 0x52001C10). There is no event risen in the event register.

    The camera interface is set to work in CCP2/CSI1 mode (CONTROL_CAMERA_RX: [20:19] CAMERARX_CSI22_CAMMODE; 0x2: Data/Clock Transmission Format (CCP2/CSI1 mode))

    The permanent 25MHz clock and the data frames are present on CCP2 interface.

    What am I missing?

    I’m following the COMPLEX_IO initialisation from TRM.

    Could be my verification method is not good?