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BQ34Z100-G1: 3 Application questions

Part Number: BQ34Z100-G1
Other Parts Discussed in Thread: BQ34Z100

Hello Sir:

We have 3 application questions as below.

1, If the pack is 12S6P, 2 cell imbalanced, how much is the impact to SOC/SOH accuracy if the cell blocks are voltage imbalanced? 

2. Is the value of the cell-impedance obtained by BQ34Z100 impedance track algorithm can be reading by host processor? If yes, please let us know the I2C command of this requirement. 

3. If maximum charging-current is 5.5A. minimum discharging-current is -100A. What calibrating-current is recommended by TI?

Please provide your recommendations for us.

Thanks a lot.

  • Hello Sir:

    Can you provide your recommendations for us?

    Thanks a lot.

  • Statham,

    1) This is an unknown value. it depends on the amount of imbalance. This is the main drawback to the bq34z design because you are working off the stack voltage and not individual cells. Ideally you are only as strong as your weakest link because the lowest cell will start to rapidly drop voltage when empty reducing the pack voltage quickly. With a 12S it will hide the effects longer, but this is riskier since the low cells could severely over discharge and be damaged. 

    2) This is not read-able via a command. you would need to unseal the device and readout the Ra table and interpret them. Please note teh Ra table is at 25C and we do not offer readable temperature compensated values,

    3) The range of the ADC is +/- 100mV. you want to calibrate at 70% of this range. At 100A you will need to "fake" the gauge current by 10X to get it in range to use. Please see the application note for high cell count/high rates. 

    thanks,

    Eric Vos