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TPS50601A-SP: Master-Slave Mode Using external clock

Kimberlee Shimizu
Prodigy 180 points
Part Number: TPS50601A-SP


Hello,

I just wanted some clarification on the following statement:

"RT pins of both master and slave device must be connected to a resistor matching the frequency of the external clock being used. See Figure 18 for reference."

This mean that the RT pin of the master and slave should have its own RT resistor to GND (two resistors), correct?

Also clarification on this statement:  

"Since the master device controls the compensation, soft start and enable networks, the factor of 2 must be taken into account when calculating the components associated with these pins."

So for example if I wanted 4ms for SS.  I would put a 20nF cap, correct?

In regards to the compensation, do I simulate for half of the load then once I'm settled on values for the compensation network, just double them?  

Thanks, 

  • +1
    TI__Genius 14540 points

    Hi,

    The statement you reference is when using an external clock only.  In this case the external clock is provided to all parallel devices and each of these must have its own RT resistor.  If you wish to use the internal oscillator of the primary device, then the RT resistor is left unpopulated, thus, making the SYNC pin an output clock which is routed to the other device.

    The published calculator shows that for a 4ms soft start a 12.44nF cap is required for a single device.  Since the soft start current is doubled in the case of two parallel devices, the capacitance must double to maintain the same time constant. Therefore, Css is 24.88nF.

    For compensation, you would need to use 2x the error amplifier gm (gmea) and 2x the power stage gm (gmps) when calculating values.  The Cout would be the total Cout of the parallel system.  

    Thanks

    Christian