CSD18540Q5B: Convergence issues with PSpice simulation of mosfets

MODEL_IMPORT.DSN

MODEL_IMPORT.zip

Actually I guess the first upload I could fix, I had the voltage source over the voltage source of the mosfet. But below is another example that I can't run.

MODEL_IMPORT2.zip

Lee,

Thanks for your interest in our devices.

Our expert in this area is out for a few days on some much deserved vacation time. He will be back in the office next week and will update you then if you can wait.

Thanks

Hi Lee,

Thanks again for the inquiry. I'm back in the office today. I will look into this and get back to you shortly.

Best Regards,

John Wallace

TI FET Applications

Hi Ray,

I cannot open any of the design or project files you included in your previous posts. Seems that there may be some files missing. Perhaps you can archive the project and resend it to me via email or private message.

Thanks,

John

model_import-2021-05-17T21-06.zip

Hi Lee,

Apologies for the mistake with your name in my last response. I am still having problems opening your simulation. I am going to consult with a colleague to see why I'm getting errors when trying to open it with either PSpice for TI or Capture CIS 17.2. We've seen some convergence problems with our FET models due to the way the parasitic capacitors are modeled in a tabulated format for better accuracy. I've had success replacing them with fixed capacitor values although it may be less accurate with this approach. I'll send you a modified model via private message to see if that resolves the convergence issues you're experiencing. Unfortunately, PSpice for TI will treat this as a non-TI, third party model, which will limit the number of probe points in your simulation.

Best Regards,

John

Ok running it now without issues with the modified CSD18540. My model is pretty simple, shown below. I'm interested in studying the switching effects. So it makes me wonder if the tabulated version is still preferable. Is there a good simple pspice model that runs well with the the TI tabulated mosfets? Ideally I'd like to run something like below but then experiment with gate resistance and also put in some parasitic inductors and such to see the effects. What are your thoughts?

Hi Lee,

Try adding a small resistor between the gate and source of the low side FET, U1. Looks like you're using this FET as a diode and sometimes PSpice doesn't like a dead short. I tried to replicate your circuit in TINA-TI (just because it's quicker for me) and had convergence issues until I added the resistor from gate to source. I tried values from 1mOhm to 1Ohm and it always converged. I created a macro from the same PSpice model available in PSpice for TI. Let me know if that works.

John

Hi Lee,

I tried this in PSpice and ran into convergence issues even with the resistor from gate to source. I also tried to increase the rise and fall times of the voltage source driving the gate-source of the top FET to 100ns and had no convergence issues. Shorter times such as 25ns caused convergence issues. I'll try some other things to see if I can get it to converge.

John

Hi Lee,

I've tried multiple things to get this simulation to converge with limited success. Replacing the bottom FET with the default PSpice diode always converges. Reducing the rise and fall times is also successful (sometimes) as is reducing the inductor value. I don't think I can do more at this point to resolve this and get you the best accuracy in your simulation. This will take longer to get to an acceptable solution.

Can you tell me more about your application? Based on your company, I'm guessing this is for a motor drive. Can you share any additional details on what type of drive and your requirements?

Best Regards,

John